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我目前在設計一個pipeline的電路,且有防bubble機制,但在設計的過程中有些問題~
& x, N6 x* b* n想請問一下大家!!5 l' q+ D( U3 W% j
該怎麼設計?
- H2 P) ]/ W( j; c% r以下是我需要的功能~
$ X, ?: V/ ~% g9 q3 I( @( h p; S | | | | | | | | | | | | | | | | | | | The next stage data full signal | | | | | | | | | DUT full signal to preceding stage | $ l j7 n/ Q% I- x
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Thereare 5 pipe stages in our pipelining design.
* ~( H5 ]- x$ C+ b* @: q. iIt means that the input data can beobserved at the output port after 5 clock cycles.
m9 o4 T- g6 Z3 M9 ^" ?2 \All the stages must be readyto proceed at the same time.
4 D. L, ~* }* T' H1 z: fWhen d_full is active, you have to keep the outputdata until d_full is disabled.
. a, h% U0 @+ \% ]6 ]/ |/ ]8 m% {If d_full is active and all the pipe stages arebusy, you have to generate pp_full to inform the preceding stages to hold data. 3 M& x4 U3 t/ ]+ b
The pipeline bubbles haveto be eliminated when d_full is active.4 Y9 h( J' q9 Y2 J: u7 r9 R$ |
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