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一般dly'event and dly='1'是不能寫在case裡面嗎?0 b$ e3 \9 {( D. Q
因編譯會出現以下訊息
, z+ ^; s$ @. n, g' O' ?' iError (10822): HDL error at CUB.vhd(70): couldn't implement registers for assignments on this clock edge- h- E, B0 [$ ^/ Y% e# V0 }) A
Error: Can't elaborate top-level user hierarchy
7 V8 F0 p; b. M# @/ C( kError: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 15 warnings
0 M8 U$ I1 |. a S1 T4 A9 N# ^6 q Info: Allocated 144 megabytes of memory during processing. t: _; v1 n& W) O! R
Error: Processing ended: Fri Oct 18 21:24:23 20134 J- r2 W @0 ?- y; L T
Error: Elapsed time: 00:00:02- F. {$ j2 \' B* Q. n6 f1 g
Error: Quartus II Full Compilation was unsuccessful. 2 errors, 15 warnings
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程序如果寫的不好,可以幫我改寫,因是自學,所以比較少機會可以看到其它人的寫法!2 F* `8 X- h$ ], v; J$ i: q; A+ |
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Library ieee;
5 G0 v+ ~, H( ^4 m9 y/ u# qUse ieee.std_logic_1164.all;% v }5 [* `4 @
Use ieee.std_logic_unsigned.all;- [- M, f2 A: z" L* X
Use ieee.std_logic_arith.all;
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c8 Q: y$ }/ E0 T/ q5 q0 kEntity CUB is
( ~$ z1 }5 i) T, SPort(8 h' l# J. ?$ e6 ^! g* g$ O
sv_ctrl,coll_manu,coll_auto,count_v2,T1I,T2I,dly:in std_logic;
8 w; y- W z( A count_clr,coll_up,coll,cold_pin,T1O,T2O:out std_logic
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end CUB;; Q$ d7 o2 e5 z/ A4 p* U
J: X# E. I0 v- ]) t# w2 Z5 UArchitecture cub_arc of CUB is( ^ i1 x- X# \ K9 r
signal d : std_logic_vector(2 downto 0);
$ {' F0 [( {2 ]5 y" i) yBegin1 i/ [& ^" A( s/ r Q9 g' n
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proce1rocess(coll_manu,coll_auto,count_v2)9 ], S% [1 I8 @
Begin
2 V2 T0 B; b4 w$ D5 I if coll_auto='0' then3 x8 S# l$ l0 @+ Z7 W7 {1 h% P
if coll_manu='0' then+ z. ]8 p, j$ ^( u9 T
if count_v2='1' then
; @2 Q3 e& K) O3 A1 x/ K count_clr<='1';
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count_clr<='0';! V( H: \3 S b' K% A
end if;
/ r1 x- }8 N. x: f) e! x! g! g. ] coll_up<='0';0 [0 d2 ]& W; V. P
coll<='0';
5 a8 M* d; g( J- J% S* g cold_pin<='0';4 R: _% _* r7 C8 |% o. [$ a
end if;. Z: V' @% Y: i9 d f
end if;
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3 m3 V* m' B9 k3 V5 w6 Z2 Q if coll_auto='0' then b# n& }, r+ a1 ~
if coll_manu='1' then
* e! m0 E2 o8 G0 X2 Q- k if count_v2='1' then
3 m, ?$ S2 x4 g( v( a8 E/ Z8 V count_clr<='1'; & w- v. o# V, w% z2 b
else
- @3 u! D: N% p6 q' ^9 S count_clr<='0';
/ `8 T' Y1 M! x( @+ T end if;
# d7 I$ `9 o- I& E. _" Y1 v coll_up<='1';
l& j# o+ \% ]3 u' f9 r coll<='1';7 e, B1 ^+ V! U" M. }5 U
cold_pin<='1';8 ~2 O8 F \) o" X0 v) Q
end if;. z8 t. e) _2 C* Q7 P
end if;
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( p1 V' k; ]0 K! Y' G if coll_auto='1' then
' z6 `# }6 l& F6 O P: f' l if coll_manu='0' then1 m( i7 |- F$ w$ [/ D7 K& u. s( ^
if (sv_ctrl and count_v2)='1' then
; S& r8 M5 b5 P) r1 C case d is
( }1 Y0 P3 g4 u1 b5 ~ when "000"=>9 T1 ^4 O4 T3 P7 ]
coll_up<='1';3 G6 @( R1 [. q& O: r
T1O<='1';
, X% C" C1 i) _- K0 X& |* C+ { d<=d+1;
1 A# m3 s3 O; k when "001"=>
$ i, b/ n4 D& u4 z; T9 Q if T1I='1' then0 x, e6 t2 u3 V0 }4 t' H
T1O<='0';
9 O* q+ k0 T7 N$ ] coll<='1';
* r3 n" v1 `) W0 S* B cold_pin<='1';
, O6 b6 V7 y6 j T2O<='1';, R( _2 V( z) X0 Z( `" c* s' H
d<=d+1;
! O7 P% s/ D( N. G, s8 | end if;
0 k( G8 @2 V: F, p; W when "010"=>
* X: \; E' p9 W$ [+ G# V$ ] if T2I='1' then
) B- |' w0 q) H+ X T2O<='0';/ F3 C2 M9 q! I- ?
coll_up<='0';
$ Q* n3 i5 J. s& ?: `" ~ coll<='0';$ ~8 t0 G1 \2 I# w1 g
cold_pin<='0';0 d% o: N$ j" j+ h x* [( K
d<=d+1;
8 \2 X% B: H8 s end if;. L6 d7 F9 e, y$ i, c
when "011"=>$ H. j, q3 S, f% Q6 H3 w' d
if (dly'event and dly='1') then! p; u1 n4 I% \( s( y
d<=d+1;
4 d3 l; j0 d M" p8 P end if;8 @5 Z( Z) U6 @, [ x: N- |
when "110"=>
* d- [( K: V" J8 }# F8 ` count_clr<='1';5 M. ~. i9 o" D
d<=d+1;
) i. q: r2 W! l, P9 U5 H+ Q# ~ when "111"=>
, b( Z' O( s: q% ] if count_v2='0' then7 h2 `: c4 `! z* ^3 Y3 @8 H! n; K
count_clr<='0';8 _3 \: |# _7 r6 l
d<="000";7 }% V& J* E: V8 X
end if;" B$ e/ s: o$ c% b
when others=>null;4 }# p' r0 J! K
end case;) W5 W( R2 V% T x2 A
end if;
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# K b+ Y+ x1 l" } end if;
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: l! R- B+ ^) h! p7 K: b if coll_auto='1' then
1 `6 ~3 z7 \9 W if coll_manu='1' then2 Q+ G6 }0 \$ \4 }5 @* p9 y
coll_up<='0';
% b" d% X0 u4 I+ b4 O* c/ c coll<='0';
: S5 \" Y: } X4 t' u+ D# e cold_pin<='0';
, l* A2 B2 c! x2 M% h end if;& _/ F; |/ d' N9 \$ W
end if;
' ?7 N$ i3 }7 R2 \1 B% z% f" hend process proce1;
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end cub_arc; |
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