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Job Title  igital verification Engineer" \4 `8 u) R5 j: w# O2 A
Job Category :Semiconductor
& F! K( @' Y. Q; b. `+ {$ G6 ~1 ]5 sLocation : Singapore6 j, v5 _; E: F4 {! U8 q
Job Type : Permanent! U x5 [2 w' ~, Y6 u! O
Job Description:2 R- K# G3 L; s- H6 y& z* {
Looking for SoC Verification Engineers Experienced in System Verilog Tools# n6 Y( @# i6 ^4 [) Z" p: s
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Responsibilities:
* H1 }/ i1 V8 G/ w/ W9 R2 m1 i% RConstrained-Random Verification using SystemVerilog.
7 Y- _( i( Q+ I. KDevelop verification environment for DUT,Write and debug tests for DUT using SystemVerilog, Perl, and C.
# B1 q1 _6 |7 b2 {* ?Develop Bus Functional Model(BFM) or using Verification IP(VIP) for tests
4 @: S" a6 U/ {1 Q8 r1 y" u+ [1 M! cDeveloping and reviewing test plans$ @5 H4 w, `' S+ m0 Z) ` D/ M
Write coverage monitors to evaluate the coverage of the DUT.2 s8 M$ b L, v6 @4 o' t
Formal verification using SystemVerilog Assertion to verify SOC or IP is plus
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Requirements:
* s- U4 I* q$ T* I: M>4+ ethernet switch background
( U/ O# O6 q9 Q# GAt least 3-year+ experience on digital design and verification- i. X5 Y" ?6 T9 @" y0 q
Experience on SystemVerilog/VMM/OVM/UVM (UVM is plus)9 C: c1 Z$ m+ G& V2 S: m8 h0 w
Familiarity with transaction-level verification at higher-level of abstractions is plus.
5 d: S5 m8 q5 T# k) F: j6 }Experiences in developing measurable verification plan.
- N* |& W) ^8 l: q8 R, ]' bProficiency in UNIX scripting languages and utilities such as csh, sed, awk, and Perl. |
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