In your verification flow, the primary EDA vendor/tool your team is using

ranica

CAD Engineer
公      司：a top 15 semiconductor company
工作地点：北京

  t# `0 a* t$ j/ jJob Description:
Collaborate with *** CAD teams to develop industry leading design flows and methodologies for analog and mixed-signal designs using nanometer technologies, with emphasis on improvement of layout productivity of analog circuits, including usage of advanced Cadence IC6.1 features, design for manufacturing (DFM), metal fill, physical verification and tapeout flows. Write scripts and utilities to enhance these design flows. Provide CAD support and methodology training to *** design and layout community. Write application notes and document ***’s analog/mixed-signal CAD flows. Work with EDA vendors to drive ***’s interest with regard to analog/mixed-signal tools.

Qualifications:
-         BSEE or above, with 3~5 years relevant industry experience.
/ ]! `: u0 H7 _! j/ B- B0 h( ~-         Solid understanding of advanced semiconductor process technologies
: z3 f, a& b" Y+ V, h-         In depth familiarity with layout of analog and mixed signal circuits including knowledge of layout effects (i.e. matching, reliability etc.) and DFM rules for advanced technology nodes
1 f: m  ^# e- }3 z4 [+ s; z-         Understanding of nanometer design rules and physical verification runsets
8 @' E4 @; b9 }% b+ ~1 [0 X4 C& D/ L-         Solid knowledge of Cadence DFII
-         Knowledge of physical verification tools like Mentor Graphics’ Calibre
3 Q, h+ i7 v+ N8 F-         Knowledge of Skill, perl or other programming languages
-         Strong written and verbal communication skills

ranica

Senior Physical Design Engineer
公      司：A famous IC company
5 u3 [8 z, J9 w% l工作地点：南京
" H9 |- `5 A5 F! ?
Key Responsibilities  
Depending on experience, key responsibilities will involve some of the following:  
0 w/ O' S7 ^+ [- uIC implementation from netlist to gdsii, with synthesis, floorplanning, place and route, timing closure, and physical verification.
1 H$ m& O# g7 c0 e9 WAs a key member of physical design team, your will work on one of most advanced and the most complex chip designed.
. j4 ~3 A6 O& T" B, N, A' iLeading a team of physical design engineers and resolving the technical related issues.  
9 n) ]6 E6 v( n6 P, z1 p5 oCrosstalk analysis, power analysis, and static timing analysis.  
Write scripts in Tcl to improve productivity.  
/ K8 g- s. @& {& |
Experience: 5+ years in physical implementation engineering  
- F. s5 p( G9 I/ j  {% Y$ K$ V  
Essential skills  
MS in EE required.&#8226roven track records of working independently on place-and-route project running and DRC/LVS/ERC/Antenna debugging skills  
  [3 n" {( w4 d- L" Y, V: r9 _Experience with Magma or Synopsys place-and-route tool set and physical design project implementation.  
Good programming skill. Capable of writing Tcl or Perl.  
4 C: E' q- a- B, s2 R+ Y/ f- jFamiliar with synthesis, static timing analysis.  
Self-motivated team worker, good verbal and written communication skills in English.  
% d) c4 c  |' v' ?Technical and team leadership proffered. Previous management experience highly desired.  
- b+ r' a, n: I9 _$ g4 XExperience with synthesis, DFT, and verification is preferred.

ranica

Senior/Staff Design Verification Engineer
公      司：A famous IC company
工作地点：上海

1 w2 l* M8 k% d$ |0 dExternal Description:
0 v* v) c' m' l. M- work closely with designers on verification test plan definition and test development
  W$ L! B% q0 q/ Y8 Y8 ^- work closely with architects on performance modeling and validation
6 v& P7 O8 [/ c5 A- regression infra development
- coverage analysis and enhancement
- behavioral model and BFM development  
- unit-T and timing gate-level verification
& Y- h# S; Q, U* P5 s7 z- develop IPs verification suites
- silicon bring up and debug support
/ Z$ ^" I+ {9 n# G  N- p
) V& A3 a3 T7 t$ X% f+ E4 bQualifications:
Must have:
6 I/ D7 T! e( O; V4 V+ f8 a2 p- minimum 4+/8+ years of ASIC verification experience
- BSEE degree or above
$ w5 D7 O, R! \+ o1 |- strong programming skills, proficiency in C++, system verilog
- working knowledge of scripting language (Perl, Python, etc.)
- working knowledge of verification methodlogies such as VMM, OVM or UVM
- good communication skill
- good team work spirit  
) o. r. }/ }! ^! U
Nice to have:
3 O% Z% G6 ~& b3 N- familiar with DTV/STB architecture, design, IP and system

ranica

IC CAD 工程师

公      司：A famous IC company
工作地点：上海
) I$ m0 ?% l  u- J+ U1 H. m8 w
. z( W: Y8 z, G1 H6 u$ a6 x: u职位描述
1、IC设计研发团队服务器的搭建与管理，保证服务器的稳定、高效以及数据安全；
2、负责EDA工具及相关license的安装和维护,优化相关环境变量及软件设置，确保设计环境的正常运作，提升自动化程度；
. @3 F# `' H# I1 p4 v3、为IC设计提供EDA工具技术支持及项目支持，使用perl,shell以及tcl等编写自动化脚本，优化设计流程，提高设计工作效率；
4、协助完善IC设计流程。
6 W3 d% M9 M; a# x# S5 {' j: ^. G
: i6 T2 {5 g( [岗位要求：
4 e' ?& `1 H( ]2 M1、计算机、自动化及电子相关专业本科以上学历；
2、两年以上相关工作经验；
" o3 {$ e+ u2 Z$ T" L5 N3、具备撰写Perl/ C-shell/TCL等编程脚本的技巧和能力；
& s% @6 b8 P2 F) `! ^4、熟悉UNIX/LINUX操作系统，熟悉多种EDA工具；
! M! l4 {- o  e: Y2 N  T5、具有IC设计软件使用经验或了解IC设计流程相关知识者优先考虑；
. z2 w# R% d# z. w4 E. E6. 具有良好的沟通能力、分析问题能力、较强的协调能力，以及团队合作意识。