In your verification flow, the primary EDA vendor/tool your team is using

sophiew

for Verification Planning on your current project

% b6 a) E& ?* l3 g" ^! RIf other (please specify), or you don’t know?

ritaliu0604

新思科技推出DFTMAX Ultra  可大幅降低矽測試成本(silicon test cost)
客戶能以更少的測試探針(test pins)提升壓縮能力(compression)達三倍
6 V/ ^, m- A+ D7 U& b# s( n
(台北訊)全球晶片設計及電子系統軟體暨IP領導廠商新思科技(Synopsys)近日推出DFTMAX™ Ultra產品，此乃新思科技電路合成(synthesis-based)測試解決方案之一環，可大幅降低矽測試成本。內建於Design Compiler® RTL合成中，並具備新推出的測試技術，DFTMAX Ultra能提高壓縮能力達3倍，能同時進行數個裸晶(die)的測試，還能充分利用測試儀設備的最大效能，以減少矽測試時間。在不影響設計目標和時程的條件下，設計人員利用DFTMAX Ultra所帶來的優勢，能滿足嚴格的品質要求，並進一步降低測試成本。  

新思科技的DFTMAX Ultra包含最新開發的技術，可有效地讓經壓縮的測試數據在可測試性設計(design-for-test ，DFT)電路中流通，如此一來可降低達成優質矽晶生產測試品質所需的數據量。該工具生成(tool-generated)架構僅需較少的測試探針(test pin)，且在進行測試時能讓矽晶以較高頻率運作。因此，設計人員能同時進行多個裸晶的測試並降低每個裸晶所需的測試時間。為了達到優質品質和實現快速周轉(turnaround)時間，設計團隊使用DFTMAX Ultra以及新思科技Galaxy™實作平台 (Implementation Platform)工具套件，可在速度、面積、功耗、測試和產出之間實現最佳化的結果。

1 P4 ~$ r* M/ P" @5 i  Y) M新思科技實作事業群資深副總裁暨總經理Antun Domic表示：「新思科技在電路合成測試的領域居於領導地位，早在2005年即推出DFTMAX壓縮技術。與TetraMAX ATPG一同運作，能讓設計人員降低測試成本同時提升產品品質。這次推出的DFTMAX Ultra 是我們新開發的電路合成測試產品，能協助設計團隊以更低測試成本來達到更高品質的目標，同時滿足更為緊湊的設計時程。」

tk02561

Lead Physical Design Engineer（Shanghai）
& ^9 z, n4 g8 Q3 s8 u公      司：One world top EDA company
$ [/ Z2 ^/ z% y4 l工作地点：上海

职位描述
, w- t0 f& }+ W# C, J7 {' L" [5 \-Perform physical design implementation, including synthesis, floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure, and physical design project management.
* ^! B1 b  _7 O- ?( L: y% i-The candidate will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed design. The responsibility includes participating in or leading next generation physical design, methodology and flow development.

职位要求
1. BS degree with 10+ years of applicable experience, MS degree with 7+ years of applicable experience in electrical engineering, microelectronics.
6 a  H  B2 n2 O/ b" L, i+ q2. Experienced with ASIC design flow, hierarchical physical design strategies, methodologies and understand deep sub-micron technology issues.
3. Solid knowledge on LP Design, DFT, static timing analysis, EM/IR-Drop/crosstalk analysis, formal verification, physical verification, DFM.
0 d( y) Y7 b# D- k4. Successful track records of taping out complex, 65/40/28 nm SOC chips.  
5. Automation and programming-minded, solid coding experience in Makefile/Tcl/Tk/Perl.
3 `) q6 e- Q, J. J0 ~1 L- S6. Self-motivated, able to work independently or as a team player, excellent verbal and written communication skills in English.

tk02561

Staff Hardware Based Design and Verification Engineering Lead
公      司：One world top EDA company
4 {9 N! p8 ?; `* s/ z* `工作地点：上海
% m, E( t- t' \) r8 |, T- t; h
Position Description:  
1. The Staff Hardware Verification Engineering Lead will be in charge of a team of field engineers to support advanced hardware based verification flow integration engagements with Cadence customers and provide easy-to-adopt packages and workshops to xx  field application engineers and customers alike.

2. He/she will focus on the technical aspects of the following hardware verification solutions for customer engagements as well as creating demos/workshops to train field AE and customers:
+ H' {/ I& ?8 g(1) xx  Palladium HW Acceleration Platforms
(2) xx Acceleratable Verification IP portfolio
: j" b* C: p- O* }  @- V(3) CVA product integration with other xx products such as Incisive Simulation and RTL Compiler for power analysis
: A# Y! @: `4 @' t" v(4) HW/SW Co-verification solutions for SoC designs

tk02561

Position Requirements:  
1. Experience:  
- Minimum experience required: 10 years  
' ~  _: w/ `* `' e- A  l, }' ?" {- Expertise in RTL top-down design and verification methodology automation are required. This includes full hands on knowledge of writing and debugging Verilog, VHDL and SystemVerilog based D&V environments.
7 n# v- o. s% \4 h# q- We would also like the candidate to have good knowledge of SoC design principles, embedded software development and HW/SW codesign and coverification.
# L3 `" V/ O0 C& e/ G- Knowledge of UNIX, C/C++, other scripting programming languages ( Perl, TCL…) is highly desired
( ]! D1 X7 X6 |4 l- Strong verbal and written communication skills in English are required  
- HW acceleration or In-Circuit Emulation or FPGA prototyping experience is a must
: H) t- v1 d0 _2 U4 c- }8 y- Hardware verification, including knowledge of HDL simulators and debugging simulations
$ t( L; n8 \; H' L. S& t/ ^4 p- Hands on experience with using design and verification languages like SystemC, SystemVerilog (IEEE 1800) and VHDL is a must.
- Knowledge of embedded systems and software development for SoCs is a plus
2. Education:  
! F0 }6 O% f& E& S, t+ `) ^/ nIdeally the person should possess the BS/BE level of understanding of CS or EE Engineering concepts  
8 z! S* P& e" n. X/ \" M- Minimum Education Required: education level of BS with 10+ years experience (or MS with 7+ or more years experience).
2 ^' Q( c# a2 G" n" ~3. Travel of 30% of the time should be expected.