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Staff Verification Engineer
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公 司:one famous IC company
6 v) J5 e* E) G0 L工作地点:上海
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' V2 |6 d, Q1 l4 _0 EQualifications ( b5 Z: @1 O) N# K& l; i
MS in EE/CS/ME.
# _6 v+ z, c) v2 Q2 cMinimum of five years experience. ' ^! x ]4 a: E/ P6 k0 E
Additional qualifications include: Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills.% ` T+ `1 o& `7 T7 y8 h( R
Candidate should be familiar with as System Verilog, VMM/OVM/UVM verification methdology.
) O- Y) n; n5 q6 ^3 x4 {" ?Candidate should be familiar with industry standard ASIC design and verification tools and flow. * _8 H" C! ]. G
Good knowledge ddr protocol and computer system achitecture would be an added advantage.
1 F1 V0 Q+ d* n6 R$ eGood knowledge of Perl and shell programming would be an added advantage.
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: y9 ]8 n3 r7 d; C8 }1 i, lResponsibilities:
- E2 b+ X' Z1 \, D. K9 @$ |-Understanding the expected functionality of designs. " x7 F! M+ F H; [# V
-Developing testing and regression plans.
; s/ k. f8 K8 d, N" a) @1 y7 o: T-Designing and developing verification environment.
, H6 o+ Y. J, Z-Running RTL and gate-level simulations/regression. ( q' _0 p: S- T' n
-Code/functional coverage development, analysis and closure.
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Requirements:
) g; ^$ I6 u4 h hExperience & Skill: 5 Years * B+ K9 [9 o8 V
-Design verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.). * n8 h7 t/ t! w- `
-Knowledge in ASIC/FPGA design process and verification tools.
7 U, Y& X6 S3 }2 r& X8 k$ \-Familiar with design and verification languages (Verilog, System Verilog, SVA etc.).
" q& C0 i; P& U9 Q6 w2 G- Scripting and automation skills (tcl, perl, makefile etc) a plus. - O! X% q5 G0 u9 q; t" t2 Z
-Familiar with C/C++.
' X; Z) L/ z6 @' l4 |+ |-Knowledge of DDR protocol a plus. 6 X4 I# Z- }) _( u
-Independent and self-managing. |
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