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大家日常設計專案中,哪項工作佔比最重?

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1#
發表於 2014-6-12 10:41:58 | 顯示全部樓層
DIP Application Engineer" l! q& `, |# B( n  |: w6 |7 n

9 e1 ^5 |. N9 f, c公      司:One world top EDA company
+ e% e9 v2 [* U6 i2 }5 G6 b8 {工作地点:上海$ t2 ]( Y7 L) n: l

. [2 Y1 r  r/ J/ t, }Responsibilities:
9 S3 B. m9 J" T0 [. Y# l! m1) Providing direct technical support to customers in presale stage to persuade customers to adopt Cadence Design IP solutions for their applications
* S2 |! ]- l9 _1 a6 m* {2) Interface with customer architects and Design IP business unit to enable evaluation of application specific IP performance and features per customer’s SOC requirements.
8 v/ ]0 `2 T7 f; F& v. u: x% n2) Working with the sales team to manage the IP activities in the region to achieve a high customer satisfaction rate and for building strong customer relationships" R: {0 i# f' c7 O
3) Providing customer feedback on new/existing requirements for Design IP usage from customers to the IP business unit., ]$ z) J' I( G4 r1 u4 v
4) Providing direct technical customer support and assistance to enable customers to successfully integrate/use Design IP in their SOC.
  i; }: B) q# t; J5) Writing application notes in situation to facilitate customer usage of the IP
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Position Requirements : 4 j3 K- W( ^: X! R5 J  Y
1)  Experience in digital/analog design and implementation of controllers/phy 9 s6 K8 D$ y7 V+ `
2)  Knowledge of serdes and backend implementation is a plus
0 M7 w5 }4 k* V3)  Experience with SOC architecture include on-chip fabric (AMBA/Sonics OCP/Arteris NOC), external interconnect protocols (e.g PCIe/Ethernet) and DRAM memory protocols (DDRn, LPDDRn), DRAM PHYs, .NAND Flash (Async, ONFI, Toggle NAND), eMMC/SD, MIPI& N( ^$ J' q5 I4 r# m
4)  Knowing serdes/analog IP is a plus - s+ Y# [( p7 `% K: O
5)  Exposure to IP-based SOC design flow and real tape-out experience.
0 I0 q# q( B. d: Y# j1 B+ r6)  Good written and verbal communication skills and problem solving skills are required. - E( v% `% v9 B8 ?2 I
7)  Ability to conduct technical meetings, presentations, seminars and training to customers and to the sales team) i" Z1 z5 e- l, u0 Y; }, y7 I
8)  Travel within AP region may be required. / _; P8 D: J6 g* u
9)  Good understanding of the semiconductor IP marketplace and ecosystem is a plus.
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2#
發表於 2014-6-12 10:42:35 | 顯示全部樓層
Staff Verification Engineer
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公      司:one famous IC company
6 v) J5 e* E) G0 L工作地点:上海
# n9 ^2 Z  c, i  I" _7 l- y
' V2 |6 d, Q1 l4 _0 EQualifications ( b5 Z: @1 O) N# K& l; i
MS in EE/CS/ME.  
# _6 v+ z, c) v2 Q2 cMinimum of five  years experience. ' ^! x  ]4 a: E/ P6 k0 E
Additional qualifications include: Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills.% `  T+ `1 o& `7 T7 y8 h( R
Candidate should be familiar with as System Verilog, VMM/OVM/UVM verification methdology.
) O- Y) n; n5 q6 ^3 x4 {" ?Candidate should be familiar with industry standard ASIC design and verification tools and flow. * _8 H" C! ]. G
Good knowledge ddr protocol and computer system achitecture would be an added advantage.
1 F1 V0 Q+ d* n6 R$ eGood knowledge of Perl and shell programming would be an added advantage.  
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: y9 ]8 n3 r7 d; C8 }1 i, lResponsibilities:
- E2 b+ X' Z1 \, D. K9 @$ |-Understanding the expected functionality of designs. " x7 F! M+ F  H; [# V
-Developing testing and regression plans.
; s/ k. f8 K8 d, N" a) @1 y7 o: T-Designing and developing verification environment.
, H6 o+ Y. J, Z-Running RTL and gate-level simulations/regression. ( q' _0 p: S- T' n
-Code/functional coverage development, analysis and closure.
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Requirements:
) g; ^$ I6 u4 h  hExperience & Skill: 5 Years * B+ K9 [9 o8 V
-Design verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.). * n8 h7 t/ t! w- `
-Knowledge in ASIC/FPGA design process and verification tools.
7 U, Y& X6 S3 }2 r& X8 k$ \-Familiar with design and verification languages (Verilog, System Verilog, SVA etc.).
" q& C0 i; P& U9 Q6 w2 G- Scripting and automation skills (tcl, perl, makefile etc) a plus. - O! X% q5 G0 u9 q; t" t2 Z
-Familiar with C/C++.
' X; Z) L/ z6 @' l4 |+ |-Knowledge of DDR protocol a plus. 6 X4 I# Z- }) _( u
-Independent and self-managing.
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3#
發表於 2014-8-5 14:47:43 | 顯示全部樓層
IC CAD 工程师2 f; H4 M0 T) g: E, c! E" V" t% H

# H0 O' f2 c2 a5 g5 C7 t5 ]公      司:A famous IC company+ j7 d( w; s) r, u7 D$ w/ _
工作地点:上海
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职位描述2 t0 I8 ^- u  ^- y4 U4 |
1、IC设计研发团队服务器的搭建与管理,保证服务器的稳定、高效以及数据安全; % Q+ G9 X! {4 \- h
2、负责EDA工具及相关license的安装和维护,优化相关环境变量及软件设置,确保设计环境的正常运作,提升自动化程度;
% C2 n: {0 T! M3 J3、为IC设计提供EDA工具技术支持及项目支持,使用perl,shell以及tcl等编写自动化脚本,优化设计流程,提高设计工作效率;% V8 O" m2 d4 u" N2 Y2 F
4、协助完善IC设计流程。 : R) N$ s* b4 J4 \% N- T/ E1 D. \

, g  U7 Y9 r& Q# u0 \3 I/ y岗位要求:
, |  i# o7 Q" C- t! D1、计算机、自动化及电子相关专业本科以上学历;
) \' \+ `# _& v) N3 M2、两年以上相关工作经验;
2 ?0 s% s& p# R. c# \3、具备撰写Perl/ C-shell/TCL等编程脚本的技巧和能力;
( {# r8 x* U! F4 K3 j4、熟悉UNIX/LINUX操作系统,熟悉多种EDA工具;
' |) v  @+ _' l& e# r9 D( _: f5、具有IC设计软件使用经验或了解IC设计流程相关知识者优先考虑;
: w: Q9 c* J+ _9 X$ G7 O6. 具有良好的沟通能力、分析问题能力、较强的协调能力,以及团队合作意识。
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