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各位:现做mixed-signal仿真,使用的工具为spectreverilog,随便做一一个电路,现在报以下错误,不知道是怎么回事,望各位指点:+ Y- H! m0 c, f+ ?/ d
该错误是在做以下操作时显示:Mixed-signal/Display Partition/All Active' [' w% q% ^' l* }
error: failed to partition the design.- ~- a1 `0 A4 l5 \
......unsuccessful.( i* F( u+ b' d' x |+ q
error: cannot create and partition the design.& h& Q7 a3 {- @& p M5 l9 z7 S
error: must fix design errors before netlisting.
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' f2 @/ n) K; r, CPS:在做混合信号仿真时,需要注意些什么?有什么比较实用的资料可以参考,多谢! |
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