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RFIC工程師門檻?要當RFIC Designer的三大條件?

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1#
發表於 2013-12-26 10:14:11 | 顯示全部樓層
Field Applications Engineer2 ?4 M1 b2 x4 x
公      司:A famous IC company
& D+ z5 q) F+ E- T% D" i, z工作地点:深圳
$ [( [0 Q: n3 m: F: o* i' J" I
( k, _- G8 a: K5 Y5 JJob Description
( M- s- E3 h1 {! wLead and manage a team of talented FAEs in supporting customer projects.  ; f& G" h" m4 H! P; b6 L, [
Design or modify PCB reference design to implement preferred RF & BB IC layouts.  
' _/ `. R& J' p  E9 fWork with engineering to implement hardware QA procedures to satisfactorily test hardware releases in advance of shipment to customers.
5 e7 X# A+ K& {: [Debug customer hardware/firmware issues and track the changes through engineering. Document appropriate ECN’s within engineering or outside engineering services companies.
! Q# c4 K$ t! Z) l) N  S/ a$ lWrite appropriate documentation to support ***’s development kits and reference designs. Create HW related customer support documents, application notes, and FAQs. 4 }. C6 u* T! @% \3 N9 {
Work with Engineering to implement hardware release standards and track hardware revision history among customers who have XX development kits and reference designs. - Z3 z$ @) f9 a) v2 y6 n) M
Work with the Sales and Marketing Teams to promote the company’s products and technology advantages.
) F* }. K8 n6 q$ F5 n! r+ b; {. HWork with the Sales and Marketing Teams to qualify the technical feasibility of new potential programs.  6 f% }; }$ G6 @5 n" J7 g9 `0 S
Work with customers to bring programs from concept stage through to production.  4 ]2 v$ P1 F& n4 C% L/ Q
Work with customers and the internal Quality team to identify, debug and troubleshoot product quality issues.' _& G3 Y3 q9 j8 ?

; x+ x) c+ W0 N$ K/ M9 q/ H9 jRequired Experience  
) G  a9 Q7 X; CBS or MS in Electronics Engineering.  4 _: R: h  x$ K
Minimum of 10 years of hardware development and a minimum of 5 years experience in hardware semiconductor applications engineering * t2 Y' c$ _: ?4 i  v! C; L
This individual must have experience working with customers in the early phases of development, and in particular, experience in defining Development Kits and reference designs is essential. $ J+ H6 r* L1 `  S. O
This individual must have experience working with customers in the early phases of development, and in particular, experience in defining Development Kits and reference designs is essential.
6 i. ^" i5 N" i0 f) ^% o! a, Y& M) nExperience with communication IC’s, networking and video products are essential. Skills include hardware design, hardware support, IC debug, RF layout, development kit, and reference design support.
& L# x9 Z+ {; Y! F1 gThis individual should be familiar with test equipment, schematic capture, and PCB layout tools, and production layout issues for mixed signal and RF systems. ; B* m; O& O$ N3 X- i& s! U
Decent English communication skills in both oral and written.
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2#
發表於 2013-12-26 10:15:05 | 顯示全部樓層
Sr Analog Designer
- f! _' Q4 `+ \& u$ ]- g7 H公      司:A leader in high performance analog and mixed-signal IC design: u$ p6 Y& I4 c+ `& G7 l& R" L
工作地点:北京
  O# c+ y: W/ H9 p; B! i
& W7 d4 z9 V3 ZEducation and experience requirement 9 a: o: g, C7 S; A+ b
o     PhD in EE, MSEE and 5+ years of and/or mixed-signal IC industry design experience; or BS and 6+  years of analog and/or mixed-signal IC industry design experience
, O1 V: I% x1 j6 P* c# f2 i7 Yo     Hands-on CMOS product design experience in two or more of the following areas 4 f. |! P0 z9 k# m1 i
o       Receiver front end, including analog front-end, demodulation, channel selection etc.   U; ^8 a" G$ t- B/ n7 t  b
o       High-precision ADC, including sigma-delta, pipeline etc * j$ P0 n  M4 P
o       High-precision DAC
0 H0 w' x* M5 X; \$ ^. h; Ro       Fully-differential continuous and discrete-time (e.g. switched capacitor) amplifier/filter design
" I' w5 t/ {* [o       High-precision oscillator/PLL/DLL   F8 }$ S, _1 O8 v* J( u( e9 P
o       Low noise voltage reference : m8 Q+ G/ _6 E, f+ S5 S
o       On-chip high-voltage charge pump
2 w$ U" T0 F5 a; m7 ]* P$ L?      Experience in system level definition, modeling and verification a plus
0 t8 ?4 E6 Y5 @. S3 {% \5 j/ a?      Hands-on experience supervising layout and post-layout verification 0 l* S0 B1 N- y5 O
?      Proficiency in tools
* @* q0 P, r( w9 R$ `' v- po       Cadence design environment
' P0 b& U$ r# Bo       Verilog/VerilogA/Matlab or other tools for system level modeling and verification  a plus
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3#
發表於 2013-12-26 10:15:56 | 顯示全部樓層
Sr Analog Designer
* [* J5 w" D- m9 \7 X+ H2 ^公      司:A leader in high performance analog and mixed-signal IC design
$ d9 |# z: g1 g& l$ P工作地点:北京
( _" h% N& O# S) C8 F+ n, L0 r% ]' }9 D4 Q* M6 o
Education and experience requirement   Q" U$ m9 X( E$ J, Q
      PhD in EE, MSEE and 5+ years of and/or mixed-signal IC industry design experience; or BS and 6+  years of analog and/or mixed-signal IC industry design experience ) W& Y6 W/ Y; U. a& D! Y6 O
      Hands-on CMOS product design experience in two or more of the following areas ) f6 E1 e) T" P# e7 m
       Receiver front end, including analog front-end, demodulation, channel selection etc. # M; Y' r9 E8 q$ G" m' O1 [; g4 _$ Q
       High-precision ADC, including sigma-delta, pipeline etc
9 k& D' [$ ]' ~       High-precision DAC
! }& B: o* l) ?& Y7 ^) Z# b" U       Fully-differential continuous and discrete-time (e.g. switched capacitor) amplifier/filter design " W1 s$ |6 c" O) g
       High-precision oscillator/PLL/DLL / [6 Q% J% x& K6 k( s$ p1 t
       Low noise voltage reference & ~) }( `7 e1 J. z
       On-chip high-voltage charge pump 2 C- G0 h2 f1 B
      Experience in system level definition, modeling and verification a plus
7 C& {$ x5 G, Z/ i      Hands-on experience supervising layout and post-layout verification
7 U& l- X5 D- H; y$ @& I8 y6 `      Proficiency in tools 5 a1 N! r0 r4 E0 k3 _! f3 M* C/ E8 I6 M
       Cadence design environment ( e) w, J2 G# K+ t0 O( D" |1 N! \* h
       Verilog/VerilogA/Matlab or other tools for system level modeling and verification  a plus
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