RFIC工程師門檻？要當RFIC Designer的三大條件？

tk02561

RFIC工程師跟RF工程師的薪水好像差了不少？
& @5 L9 W9 n+ Q4 [: d1 t' h
8 Z1 Q- n& F1 R以上都只是入門的門票而已？

哪項對你目前而言，殺最大？

ranica

Sr. RF Tool Engineer
公      司：A famous IC company
工作地点：深圳
  t: R* i$ Y0 m: h
职位描述
- Support Qualcomm 2G/3G/4G chipset customer for design-win projects
- Help chipset OEMs to understand QCT software/solution, give customers training of QCT products
3 P. N- G$ t( L- Help/direct customer engineers to resolve the issues in using QCT solution no matter it is QCT problem or not
8 C8 Y- ]1 K+ `; @$ ?/ M- Play consultant/expert role, trouble shooting, identify problem reported by customers, analysis and report issues to developer team, help developer team to narrow down the root cause and fix problems
5 A0 L/ X! ^* S# y+ j- Familiar with usage of wireless test box such as CMW500, Anritsu 8820 or Agilent 8960, spectrum analyzer, signal generator, Oscilloscope etc
- Familiar with 3GPP RF test spec and production test requirement
- Familiar with factory tool development, e.g. RF calibration tool, RF test tool, etc…
6 |# e/ u. O: t6 a- M6 n! A- Strong C/C++ programming skill and debug skill
0 r' M# _! a7 a. U- Strong experience in ASM/C/C++ programming.
: I+ f" s! D  K9 S8 r- Good knowledge on digital communication system including GSM,CDMA2000, WCDMA, TD-SCDMA or LTE is highly preferred.
- Good knowledge of RF and analog circuits is highly preferred  
! O. ]; C- T8 y% ]+ L. k( Z/ Z- ET tool development experience is highly preferred
- Strong English communication and interpersonal skills, high motivation
4 [, w1 w5 }& y! H+ r8 x* N- The ability to learn quickly, and must be a self-starter

ranica

staff system engineer
1 D) ~" w! X2 a: J4 T9 s* k3 L公      司：A famous IC company
5 Y. G4 z" R# c* F  x- f, n工作地点：上海
- W4 D: w' ~1 t$ f5 ?: `
( G* G% R0 b- S( Q: QJob Description:
The platform engineer at ***will be responsible for systems DVT (design verification test) and HW design for advanced RF/Mixed signal SOC products. The work includes test planning, automatic test (ATE) development, systems DVT, FPGA verification, SW regression testing and HW designs. The platform engineer will be working closely with a world-class team of Systems engineers, RFIC designers, ASIC engineers, SW engineers and marketing personnel.. As a platform Engineer within the team you will be contributing to the development/test of world leading tuner/mixed signal chips in a dynamic, fast-paced, and growing environment. The preferred applicant needs to have extensive knowledge of RF receiver/transmitter and demodulator in system design, verification and applications.

9 L( [' U/ N: b: b1 r6 `/ a2 zRequired Skills:
; z3 E( r( a, w% ]·         Systems HW design and verification test experience in one or more of the following areas: analog/RF; digital SOC test; FPGA.
·         RF/Mixed signal IC bring-up, trouble-shoot, test and characterization experience
·         PCB design skills (schematic design and extensive layout knowledge for RF/mixed signal ICs)
# }" S5 b6 Z/ ]6 \) b* S·         Soldering skills and HW design prototype/debug skills
·         SW programming skills of Visual Basic and LabView or equivalent are required.
·         Strong lab test skills with typical test equipment like network analyzer, Oscilloscope, signal generators, and spectrum analyzers
·         FPGA verification experience is highly desired
# C, N% b# ~0 F+ s6 f·         RF system block-level testing (LNA, Mixer, VCO, PLL, etc) experience is highly desired
·         Experience with documentation (Test report, test procedures, application notes) Good written and spoken English communication skills are necessary
0 L, Z( M5 Q  x- R1 V·         Good spoken and written English communication skills

tk02561

staff system engineer
公      司：A famous IC company
, t8 c* W( S! y* R2 E# [* u: F工作地点：上海

' k$ ?* C6 L# s# s) G1 K2 C  eJob Description:
The platform engineer at ***will be responsible for systems DVT (design verification test) and HW design for advanced RF/Mixed signal SOC products. The work includes test planning, automatic test (ATE) development, systems DVT, FPGA verification, SW regression testing and HW designs. The platform engineer will be working closely with a world-class team of Systems engineers, RFIC designers, ASIC engineers, SW engineers and marketing personnel.. As a platform Engineer within the team you will be contributing to the development/test of world leading tuner/mixed signal chips in a dynamic, fast-paced, and growing environment. The preferred applicant needs to have extensive knowledge of RF receiver/transmitter and demodulator in system design, verification and applications.
" V8 ?3 T( x! K3 y7 H8 W
Required Skills:
" v+ T1 i& D8 U! p) x·         Systems HW design and verification test experience in one or more of the following areas: analog/RF; digital SOC test; FPGA.
·         RF/Mixed signal IC bring-up, trouble-shoot, test and characterization experience
3 O+ m; P9 F, E·         PCB design skills (schematic design and extensive layout knowledge for RF/mixed signal ICs)
( Q9 y0 J* a/ w( d3 C. x9 p3 n·         Soldering skills and HW design prototype/debug skills
& J  }* z; G' W·         SW programming skills of Visual Basic and LabView or equivalent are required.
·         Strong lab test skills with typical test equipment like network analyzer, Oscilloscope, signal generators, and spectrum analyzers
6 B( i+ K* P7 `4 Q·         FPGA verification experience is highly desired
·         RF system block-level testing (LNA, Mixer, VCO, PLL, etc) experience is highly desired
( C5 Y% W8 B  g0 y·         Experience with documentation (Test report, test procedures, application notes) Good written and spoken English communication skills are necessary
6 F5 X; V' x: y5 G2 F4 T5 q·         Good spoken and written English communication skills

tk02561

Analog Design Engineer/Lead
( V. p9 w! x5 X$ e8 s' e- Q+ R8 D公      司：A microelectronics company
' Z- n, E% l( r. L  S+ ]+ k. a工作地点：深圳

Responsibility:
+ L! A( D( Q  N# v7 P$ a& b2 P% C1.Responsible for analog IC designs, simulations, verifications and layout supervisions.
( U- G& l. E9 Q' |$ j9 i2. Establish the analog design methodology to ensure quality and IP reuse.
3.Discrete IC definition, IP integration, implementation and project coordination.
8 ?2 D) P) z! U; X! N! }0 `
Requirements:  
/ g" g6 S# J! M6 l1 F1. MS/Ph.D. in Electrical Engineering
) S, e( [2 L2 Y2. At least 5+ years of experience in analog IC Designs.  
4 d$ {4 W$ S9 i  K, k& s3. Familiar with PLL, ADC, DAC, OP, Class D, Power Manager IC.  
7 P/ K! s7 o! e& Y1 Z" l! `4. Familiarity with laboratory equipment (oscilloscope, spectrum analyzer..) is a must.  
  ?2 f4 X" V$ h2 h5. Good team work spirit, easy to cooperate with team members.

tk02376

Sr Analog Designer
/ x& \+ E# z9 C! h1 k公      司：A leader in high performance analog and mixed-signal IC design
; D( j9 t; @1 h; d工作地点：北京

Education and experience requirement
  N: T  c0 ~$ W: o7 ]0 S7 U      PhD in EE, MSEE and 5+ years of and/or mixed-signal IC industry design experience; or BS and 6+  years of analog and/or mixed-signal IC industry design experience
( E! x/ Y1 ^: I- @' l  z) ^      Hands-on CMOS product design experience in two or more of the following areas
       Receiver front end, including analog front-end, demodulation, channel selection etc.
       High-precision ADC, including sigma-delta, pipeline etc
       High-precision DAC
       Fully-differential continuous and discrete-time (e.g. switched capacitor) amplifier/filter design
5 b0 u( ^; c: f       High-precision oscillator/PLL/DLL
: J# X2 s$ `% q) v/ s3 K9 D0 Q       Low noise voltage reference
: I5 r8 A& Q4 L6 [       On-chip high-voltage charge pump
      Experience in system level definition, modeling and verification a plus
      Hands-on experience supervising layout and post-layout verification
      Proficiency in tools
       Cadence design environment
5 R: C6 Y' D/ H# z% @; l8 w8 g% R       Verilog/VerilogA/Matlab or other tools for system level modeling and verification  a plus

tk02376

Sr Analog Designer
公      司：A leader in high performance analog and mixed-signal IC design
* a, |2 v* U) A工作地点：北京

Education and experience requirement
o     PhD in EE, MSEE and 5+ years of and/or mixed-signal IC industry design experience; or BS and 6+  years of analog and/or mixed-signal IC industry design experience
, f2 ?5 y1 J3 D9 wo     Hands-on CMOS product design experience in two or more of the following areas
+ f" _$ L! Z& Mo       Receiver front end, including analog front-end, demodulation, channel selection etc.
, p, \. U* @, [3 F  ^- F- ?, i& ko       High-precision ADC, including sigma-delta, pipeline etc
8 U/ M5 J! x3 m, Oo       High-precision DAC
- O0 Y1 l) r9 h3 s( `* J- ]& Vo       Fully-differential continuous and discrete-time (e.g. switched capacitor) amplifier/filter design
o       High-precision oscillator/PLL/DLL
' A' t/ e, z9 T7 L  \: Z5 A/ so       Low noise voltage reference
% s' V) d; |( c7 E" R1 G4 N! O7 Co       On-chip high-voltage charge pump
: g/ \  T7 W  Y+ B- G$ ^?      Experience in system level definition, modeling and verification a plus
?      Hands-on experience supervising layout and post-layout verification
3 z% x4 p9 ]/ d* j1 e' f+ {- @?      Proficiency in tools
' k8 V. u0 O3 N( ^1 g! Z% R4 Qo       Cadence design environment
o       Verilog/VerilogA/Matlab or other tools for system level modeling and verification  a plus

tk02376

Field Applications Engineer
/ x  B/ E6 q9 E* ?4 K, K( r公      司：A famous IC company
0 A( o; ?% s4 H工作地点：深圳
0 t' E. \( [! m  ^5 b. Y
+ z$ n$ I3 h4 }5 ]Job Description
4 k/ R: B5 ]$ s: K3 j+ FLead and manage a team of talented FAEs in supporting customer projects.  
' w3 z  z7 N' C4 b- eDesign or modify PCB reference design to implement preferred RF & BB IC layouts.  
Work with engineering to implement hardware QA procedures to satisfactorily test hardware releases in advance of shipment to customers.
Debug customer hardware/firmware issues and track the changes through engineering. Document appropriate ECN’s within engineering or outside engineering services companies.
Write appropriate documentation to support ***’s development kits and reference designs. Create HW related customer support documents, application notes, and FAQs.
4 H8 n: l1 L$ xWork with Engineering to implement hardware release standards and track hardware revision history among customers who have XX development kits and reference designs.
9 h7 h- J3 L2 n; _- @Work with the Sales and Marketing Teams to promote the company’s products and technology advantages.
Work with the Sales and Marketing Teams to qualify the technical feasibility of new potential programs.  
Work with customers to bring programs from concept stage through to production.  
9 j; J& M' e4 hWork with customers and the internal Quality team to identify, debug and troubleshoot product quality issues.

Required Experience  
BS or MS in Electronics Engineering.  
" `0 B6 h0 r; Z) K8 EMinimum of 10 years of hardware development and a minimum of 5 years experience in hardware semiconductor applications engineering
# f: z: `% P# `% iThis individual must have experience working with customers in the early phases of development, and in particular, experience in defining Development Kits and reference designs is essential.
This individual must have experience working with customers in the early phases of development, and in particular, experience in defining Development Kits and reference designs is essential.
4 S6 L0 u2 o# r7 d! L6 x/ uExperience with communication IC’s, networking and video products are essential. Skills include hardware design, hardware support, IC debug, RF layout, development kit, and reference design support.
$ a) K# a. p6 a5 N6 ~This individual should be familiar with test equipment, schematic capture, and PCB layout tools, and production layout issues for mixed signal and RF systems.
4 l1 \0 S8 K' K" m  w, Q* {7 fDecent English communication skills in both oral and written.

ranica

无源器件/结构设计工程师
公      司：a fabless semiconductor company
! i; j  c5 `8 U工作地点：北京

8 _* H2 l  ^6 {$ k( G7 ?" t职位描述：RF PA及Switch产品中所需无源器件/结构设计  
) Z& q7 T) Y" j; ^1 }
5 X$ D7 Q( S) |微波/电磁场知识背景；  
射频无源器件/结构设计经验，包含但不限于：集成平面/立体电感、电容、耦合器、Transformer、Hybrid、功率分配/合成结构等；  
了解LNA、PA、Switch等射频电路的工作原理；  
熟悉常用设计软件（ADS，Cadence）及常用测试设备（VNA，SA）；  
9 _/ |! P/ T  H& l6 f2 K- n* `若有SAW、BAW、FBAR滤波器的开发经验，加分；  
: J4 L  U, M1 k' `若擅于专利分析、专利申请撰写并熟悉专利事务流程，严重加分。

ranica

RF PA设计工程师
公      司：a fabless semiconductor company
工作地点：北京

职位描述：RF PA/Switch新项目研发  
职位要求
  
  }' |& R+ |0 O  }& ?% b射频大信号集成电路研发经验，熟悉半导体（Si,GaAs,GeSi等）工艺制程；  
相关知识背景：微波射频/电磁场、模拟电路、信号与系统、通信系统；  
/ F, {& e5 p) z8 w  J8 S熟练应用常用设计软件（ADS，Cadence）及常用测试设备（VNA，SA）：非常看重射频实验室动手能力，射频测试中分析和解决问题的能力；  
熟悉射频发射机前端架构，了解各模块指标要求，若对前端架构有独到见解，加分；  
6 m, I8 K! @9 T5 E9 S) c若有CMOS/SiGe/SOI PA设计经验、新结构PA设计经验，加分；  
, `  g9 x, ]; w$ p" i% V若有高效率PA、高线性PA设计经验，严重加分；  
若有关于多模多频段（MMMB）PA的新结构、新想法，严重加分；  
/ I) b7 B& ~& Q  m8 ]6 O若有RF MEMS、Tunable Impedance Matching、先进封装技术等相关经验，严重加分。

ranica

Principal AMS Physical design engineer
公      司：One world top EDA company
工作地点：上海

) j( r  D5 G5 M& j; X职位描述
1 b  A4 W: V' R5 p9 VSkillful capable of physical design of Analog and mixed signal area: Matching sense from transistor, Resistor and capacitor, Power and Ground coupling, Signal path from Differential pairs, etc, if knowledge on digital blocks P&R prefered.
) H5 I' `  o; Xdepth knowledge and hands-on experience on AMS CAD support, such as write Scrips to support PDK(pcell, call back), ams back-end stuffs, including Skill language, Perl, verification runset improvement etc  
* h; a( n' W8 G& D# A& zProficient with xx layout tools specifically Virtuoso XL and Assura (xx 6.1 experience a plus)
' [9 U2 \* G/ C7 G8 oexperience in 65 nm and below analog CMOS layout, verification (DRC, LVS), and top integrated tapeout to foundry
ability to coordinate with the other analog IC circuit layout,  ensuring robust, efficient, consistent and successful delivery of analog IC circuit layout.
fundamental understanding of IC design technology and process/methodology  
skilled in Analog IC top level chip assembly including floorplanning and block layout
$ u2 \$ E/ Q3 {4 W: w3 \5 Nedicated experience on key macros is prefered: SerDes, High speed/high resolution Data Converters; High Speed PLL''s; Low Noise Design;
hands-on experience conducting DRC/LVS analysis and recommending appropriate solutions
, ~$ R% Y# K) @8 f: U% ]) Nsolid understanding of IC design technology and process/methodology in AMS layout

" j3 Z0 T) y' U; o+ L- d/ o3 }Position Requirements:
BSEE degree with >6+ years of applicable experience in advanced analog and mixed signal design industry. Essential that the individual demonstrates strong communication, verbal and written, and project management skills. Requires very good communication skills in English and Chinese.
, T, s2 Z* P5 e" o& _& z      
4 [% Q% R/ K; n/ T% O, MCompany Info Type:
7 T$ |5 r" a" n" A2 G Global Default
  D9 J; ]8 r0 f$ z$ V0 {# w8 @  
% f$ a: S3 G" M6 j4 H  l- zCompany Information:
' o8 }) H" e2 A7 s  F xx is the global leader in software, hardware, and silicon IPs that is driving the transformation of the electronic design automation (EDA) industry. This application-driven approach for creating, integrating, and optimizing designs helps customers realize Analog & Digital ICs , System-On-Chip devices, IP and complete systems at lower costs and with higher quality.

ranica

资深硬件工程师
公      司：A Chinese integrated solution supplier
工作地点：深圳

( q( S* z6 s8 F6 y6 l$ T# `职位描述：
% N2 M; d0 z( k: B% H4 h1.    电容屏触摸方案硬件应用设计，硬件应用问题分析及解决；
5 ?" m& W& s4 |3 `$ U3 o2.    触摸传感器分析及研究；
+ e2 I( x7 J. F. O3.    日常团队协调及项目跟进工作。
/ ~: _1 s; \2 |( N  `% B
( j, P. H' ?7 O: R( E任职要求：
% S: Y. y& o3 B* d& }& P; N1.    微电子、通信、自动化、数学、物理等相关专业全日制本科以上学历，3年以上工作经验
/ P, j5 }8 I/ D3 N0 `2.    具有良好的模拟电路与数字电路基础知识
3.    具有信号与系统，数字信号处理等专业背景尤佳
& n0 l8 m7 f% V0 c1 ^, d. B) ^4.    工作认真细致，主动性强，能承受一定工作压力，具有良好的语言和书面表达能力
6 C- q  L# t; [- V! \/ s* ~5.    英语四级以上，可熟练阅读英语资料
6.    满足以下任一项目者可优先考虑：
' z1 ~4 Z1 `2 X" a8 l1)    从事过电容屏设计分析工作
7 w: a7 K$ E% v+ V8 x8 `& F2)    从事过微弱信号检测与处理工作
0 o% U1 h, s; _% L3)    熟悉FPGA/嵌入式系统工作原理并做过相关开发工作
4)    使用Matlab/Simulink做过电路/信号/控制/数学建模与仿真
+ z! j  I3 Q: {5)    使用SPICE类仿真工具做过电路建模与仿真

ranica

模拟电路高级工程师
公      司：A Chinese integrated solution supplier
+ u! d6 f, M" K; C, Q工作地点：深圳

岗位职责：
1. 微弱信号检测电路研究；
5 Y, A/ I& ~; y! ^" x$ ?) R2. 芯片方案原型平台设计与调试；

任职要求：
: e3 x2 |- ?$ t% l, a1. 本科及以上学历，2年以上相关工作经验；
2. 通讯、电子、自动化、物理或数学专业；
5 D' I5 ^+ }1 Y- G3. 思维灵活，有创新精神；

innoing123

资深硬件工程师
公      司：A Chinese integrated solution supplier
* z) D4 P+ M! Q6 j" I, u工作地点：深圳

职位描述：
/ V/ X6 W0 T: Y% n/ i1.    电容屏触摸方案硬件应用设计，硬件应用问题分析及解决；
' m2 s# U! x+ h' m. U! j1 U0 _2.    触摸传感器分析及研究；
3.    日常团队协调及项目跟进工作。

# c5 Z; c5 w6 f6 N( a$ o8 g任职要求：
5 b/ A9 T. v# l1.    微电子、通信、自动化、数学、物理等相关专业全日制本科以上学历，3年以上工作经验
7 a5 {; D3 l3 M% p  B' h2.    具有良好的模拟电路与数字电路基础知识
3.    具有信号与系统，数字信号处理等专业背景尤佳
5 L0 O  K0 m, K  u. ^9 `% V% f4.    工作认真细致，主动性强，能承受一定工作压力，具有良好的语言和书面表达能力
% ]9 Z) }5 {/ ]+ O/ I6 n5.    英语四级以上，可熟练阅读英语资料
6.    满足以下任一项目者可优先考虑：
1)    从事过电容屏设计分析工作
2)    从事过微弱信号检测与处理工作
- N0 d+ q3 c$ M" H4 L3)    熟悉FPGA/嵌入式系统工作原理并做过相关开发工作
4)    使用Matlab/Simulink做过电路/信号/控制/数学建模与仿真
4 Y3 y+ M7 l& s# j5)    使用SPICE类仿真工具做过电路建模与仿真

innoing123

模拟电路高级工程师
公      司：A Chinese integrated solution supplier
+ y8 k/ c. p: G9 a  v工作地点：深圳
' }7 m  M1 p9 o' I
* s0 V+ \6 |# Z; M5 L岗位职责：
1. 微弱信号检测电路研究；
2. 芯片方案原型平台设计与调试；

任职要求：
# X) B$ x) _/ U2 D6 d" p5 q1. 本科及以上学历，2年以上相关工作经验；
; Y4 [# {8 p) s/ v! O% M& v2. 通讯、电子、自动化、物理或数学专业；
3. 思维灵活，有创新精神；

innoing123

项目经理
公      司：A Chinese integrated solution supplier
. T: ], k6 Z* N! p工作地点：深圳
. V, A) G% B1 ^
0 r% q2 Z; \/ n职位描述：
1、负责完成电容触控、可穿戴设备、智能sensor领域的芯片固件方案；
; C* S5 b  A$ X  N2、制订项目计划并负责跟进，安排团队成员工作；
+ T" k1 [# T% u3、分析市场需求和产品功能定义，协调跨部门工作；  
$ p: S) k1 c0 n1 l: T4、参与硬件方案的设计和评审，负责系统优化；

  p# R- v  B9 P' z任职要求：
8 r* g  u, O5 F7 V1、电子信息、计算机等相关专业，重点院校本科或以上学历；  
7 H1 p4 D: _( s9 c1 M3 m' k2、3年以上芯片固件开发经验；  
3、熟悉数据结构、掌握一些常用的算法分析和设计方法；  
8 Y5 ~  _3 c- R! i: L$ n7 U* @4、良好的沟通表达能力和团队协作能力

globe0968

Senior Design Manager
公      司：A famous IC company
8 H* Y( t' R! B1 a6 B/ o工作地点：上海
; ~% U- p+ a( ]# r+ p  H* r
Duties  
        Analog IC circuit design, simulation and verification  
        Design analog products and blocks such as high current, high voltage DC-DC etc.  
- k$ H$ F! ~& Z5 j0 p        Design of the switching power IC, Charger, Load switch etc.  
& E1 {  e+ X1 {: S        Evaluation, simulation and analysis of power architectures and circuit topologies  
        Mixed-signal circuit design, verification  
        IC layout including floor planning, DRC, LVS, and LPE  
# G' ?- @! x7 P3 ?4 r        Work with application and testing engineers to define optimal characterization and testing solution  
* Z* {) W3 `' N6 d: g# M        Work with product definers and product engineers in full product development flow  
        Work with product line to coordinate/lead projects, accurately scopes out length and difficulty of tasks and projects. Establishing clear directions and set stretching objectives
        Building and creates strong morale and spirit in his/her team.

. n. r/ E% e0 O3 NRequirements  
        Minimum 10 years direct DC-DC IC design experience, with MSEE or above degree  
) x3 c" `6 `. b/ B3 s        At least 5 years  leadership experience in leading a mid-sized team  
5 a% z, [, I, z1 F        Strong knowledge in analog CMOS and Bipolar IC design  
7 }1 S, p/ v. X2 K3 C( B" e        Working direct experience with switching power supplies, DC-DC converters, Battery charger,  and their various topologies  
7 p4 a  `1 ^7 |6 |8 o' u        Theoretical understanding of the power electronics, switching power supply topologies  
        Prior experience with power management related IC design a strong plus  
        Knowledge in analog IC layout  
        Matlab/Simulink/VerilogA or other behavioral simulation expertise a plus  
        Result driven and can effectively dealing with ambiguity  
6 r5 h2 C  Y' D$ ?        Excellent written/oral communication and presentation skills.   
        Understanding others, picks up the sense of the group in terms of positions, intentions, and needs, what they value and how to motivate the group.

ranica

analog engineer

! O* Q9 _8 N, p# ~( H1 \2 b9 L7 A公      司：a top 15 semiconductor company
工作地点：上海

/ ^: n( w; T6 l- R% I2 ZJob Description:  
Take charge of Key IP development for analog/mix-signal IC design project ensure the quality;
* Q: r6 }3 y& K# DProvide technical guidance  to layout; application and evaluation teams;
* N" l8 Q8 V" F2 |; dEngage with the whole project team to understand the product requirements/block requirement, and provide insights of the technology trends;
Deliver the design documents including the design SPEC, review files, evaluation plan
+ P. U, V/ j9 R" ?% ICapable for debugging and bench evaluation
' J; t& b3 l0 K2 Y! b
; \: \* N$ w- l  HRequirement:  
Solid understanding on analog circuit analysis, verification and IC design technology
( t. E3 a# P. a% `$ c" B) f' mExperience using analog simulation tools  
Good silicon debug capability
Excellent verbal and written communication skills  
Ability to work effectively within a team environment  
& P$ u) R. A, H2 H: Y  
Qualification:  
' g$ G! E3 f( I- i6 T' _3 W* cMS degree with 3+ years experience in IC industry
ADC related products experience is preferred

ranica

analog engineer
& j: x: P+ K; ^( q7 V公      司：a top 15 semiconductor company
工作地点：上海

/ M' G, w1 Y5 {" q& A; i6 OJob Description:  
Take charge of Key IP development for analog/mix-signal IC design project ensure the quality;
Provide technical guidance  to layout; application and evaluation teams;
1 r6 I3 x# l$ I8 r$ u& p/ CEngage with the whole project team to understand the product requirements/block requirement, and provide insights of the technology trends;
) ]4 ?6 x5 ~0 F. c7 |# RDeliver the design documents including the design SPEC, review files, evaluation plan
Capable for debugging and bench evaluation

Requirement:  
Solid understanding on analog circuit analysis, verification and IC design technology
Experience using analog simulation tools  
Good silicon debug capability
" ]3 h& u4 r: I  PExcellent verbal and written communication skills  
; i0 I) ~4 C( V9 B; g. UAbility to work effectively within a team environment  
& t/ ?9 {& `& _. |& ^  
Qualification:  
MS degree with 3+ years experience in IC industry
6 P7 ~8 x! Q1 S. z1 J9 v9 jADC related products experience is preferred

ranica

Staff Analog Design Engineer
公      司：one famous IC company
; _  ?+ e# U& @# Q! F工作地点：上海

5 I) h9 E! I* A* U  kResponsibilities:  
--Work with design team for new product development & assist layout designers with product layout, conduct lab experiments and bench testing and evaluation;
--Support test & product engineer with chip debugging, failure analysis, characterizations and product release efforts. Assist vendor to support ongoing product development.
5 G- M9 j' t" X! d
Qualification:
--Minimum BSEE/MSEE preferred;
--4+ yrs. of experience on analog IC design area;
( r  v1 g, D0 W' H$ ^* R--Knowledge of MOSFET physics, semiconductor process and layout;
) ?2 c8 s0 I: P; l9 V, g; z--Experience in analog blocks design, such as voltage reference, opamp, comparator, etc;
--Experience in PLL design is must to have;
" I9 h6 l' c4 e& d--Familiar with CAD tools, such as schematic capture, SPICE simulator (or equivalent transistor level circuit simulator) and Virtuso;
--At least one design finalized in silicon preferred.