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【工作內容】
4 C, S( U" t5 Z ~6 E: ^先進製程與模組開發 (DRAM/ Flash/ Logic)
. P- r, h1 t8 |9 q8 s- Photolithography (e-beam, EUV, OPC/RET, Photo Resist Materials),6 G' d# c6 d5 `/ B& @3 U" P
Dry Etch, Cleaning & CMP, Diffusion, Ion Implantation, Metallization,
2 [) j2 G/ t1 H+ k8 | Metrology & Inspection, etc. l$ W5 r& r0 `
- Device Isolation, Transistor, Capacitor, Dielectric
; v( I- m4 f( P3 B- m- High-K/Metal Gate, SiO2/SiON Gate Dielectric
/ F8 R# k2 n& D4 f, n3 S- Low-K, Interconnect, etc.5 C! N7 n* i1 p8 u4 @! C3 N
※ OPC: Optical Proximity Correction (Comput. Litho): [+ L- U7 {1 E9 \* D
MPC: Mask Process Correction
! w2 H! D" n, p) [3 C- L7 T- S7 g* G8 {: U+ Y, c" ]) S$ [ J+ ]" ?
FEOL/BEOL 製程整合 (DRAM/ Flash/ Logic)
: C% q9 H3 {1 j+ C s新型記憶體: PRAM, STT-MRAM, ReRAM0 H5 w) ~2 k& F X
TCAD/ECAD. y* V+ g+ W3 X% }
- Process & Device/Material Modeling, Circuit Compact/Reliability Modeling
: w7 N0 J; c4 [" }; o0 V2 t1 S, [8 P- Circuit Simulator Development: \7 ?8 x: A. O. s& _, N
- System-Level Modeling/Simulation, Virtual Platform, HW/SW Co-Design2 q: @+ w3 G! x2 p, w# a
- Simics/CoWare/SOC Designer UserMemory Controller/Memory Architecture/
+ I6 D( E R# e n8 `9 B" @& w: n SSD Research Experience |
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