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【工作內容】) x# X# j1 |5 W, ^ A
先進製程與模組開發 (DRAM/ Flash/ Logic): c5 z+ e- z0 o4 ]8 D2 o
- Photolithography (e-beam, EUV, OPC/RET, Photo Resist Materials),
+ t0 @, e- r( O& U/ L; b% T6 W6 ?* S Dry Etch, Cleaning & CMP, Diffusion, Ion Implantation, Metallization,
$ A ^' n) M g9 u. c% f1 N8 u Metrology & Inspection, etc.
. a/ d' V: m4 _0 Q- Device Isolation, Transistor, Capacitor, Dielectric3 B0 D4 x2 J3 n [8 b; g- p
- High-K/Metal Gate, SiO2/SiON Gate Dielectric/ U/ ~8 w0 b9 L) u/ l, x- {, }; e
- Low-K, Interconnect, etc.* U( J# E; {8 P; i
※ OPC: Optical Proximity Correction (Comput. Litho)7 Z4 w' X0 Q! e: S
MPC: Mask Process Correction
- i/ o, Q9 Y' L7 ~! ^& ]2 S2 ]& {, i( u# n5 c* `& E& k% H) u
FEOL/BEOL 製程整合 (DRAM/ Flash/ Logic): _) ], m G# z3 \
新型記憶體: PRAM, STT-MRAM, ReRAM% t: c. p4 \1 [3 T: p
TCAD/ECAD4 k g/ e) t/ b: I* p
- Process & Device/Material Modeling, Circuit Compact/Reliability Modeling
$ ~6 O; A1 F( {1 b# h$ q4 p- Circuit Simulator Development
; c' I. I/ m9 T$ s- System-Level Modeling/Simulation, Virtual Platform, HW/SW Co-Design
7 O4 Q; i# Z+ \7 y: N- a- Simics/CoWare/SOC Designer UserMemory Controller/Memory Architecture/1 a4 v. J. k8 S. `+ H7 O
SSD Research Experience |
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