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【工作內容】! I5 j7 L1 p6 w: H# ~5 J
先進製程與模組開發 (DRAM/ Flash/ Logic)5 } z, {0 s* Y
- Photolithography (e-beam, EUV, OPC/RET, Photo Resist Materials),5 ^# k" b2 {' @1 c( U* D7 t$ q' f1 {
Dry Etch, Cleaning & CMP, Diffusion, Ion Implantation, Metallization,
* k1 j) y( c& q! F Metrology & Inspection, etc.0 V% A" z. B9 K; B/ b
- Device Isolation, Transistor, Capacitor, Dielectric
7 e1 O4 W3 I( Q5 N0 B2 k( {- High-K/Metal Gate, SiO2/SiON Gate Dielectric3 M3 y5 G2 R" h# P/ [$ [ i( H
- Low-K, Interconnect, etc.: w" s3 d; m7 o% ]
※ OPC: Optical Proximity Correction (Comput. Litho)
# z2 ]+ _* m4 ?2 H! ~' M5 Q$ R/ ? MPC: Mask Process Correction
6 p0 n9 P, G/ f _
5 A' B7 @3 J, Z* d1 `0 N% CFEOL/BEOL 製程整合 (DRAM/ Flash/ Logic)# H6 t2 c' Z! o% \# F& K
新型記憶體: PRAM, STT-MRAM, ReRAM
. k8 ~% c& R HTCAD/ECAD% j d1 Y0 K5 f- j
- Process & Device/Material Modeling, Circuit Compact/Reliability Modeling5 q# l# r' W2 m4 L' Q
- Circuit Simulator Development
3 K! ^. q" u& i, P; o1 H- System-Level Modeling/Simulation, Virtual Platform, HW/SW Co-Design
, x. G! d7 @1 U+ f( p2 }/ R- Simics/CoWare/SOC Designer UserMemory Controller/Memory Architecture/
$ e+ c. ]. R6 P; x. g, E, U SSD Research Experience |
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