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The Apache Technology Forum is a comprehensive one-day technical seminar for chip, package and system designers to learn how Apache's innovative power analysis and optimized solutions enable power-efficient, high-performance, noise-immune ICs and electronic systems. This interactive forum features industry leaders sharing best practices and real design examples of proven methodologies that address critical power and reliability challenges in advanced node designs. Deep technology tracks will focus on practical solutions to meet the power budgeting, power integrity and power induced noise reliability needs of 28nm and 3D-IC designs. For those unfamiliar with Apache, this is a chance to learn what we have to offer. For designers who know Apache, this is an opportunity to stay up to date with our award-winning low-power technology. 5 ^% m. U1 ?0 s6 R7 X( \
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4 a8 p" | g% [8 i- A, g/ N2 {* }" PApache technology vision and roadmap
3 Y/ F, N1 d0 F& B# {4 Z" dANSYS introduction ( ?- f; y/ a+ f0 j$ p
User presentations on low power, reliability and Chip-Package-System applications # \5 G9 m1 j+ j1 d t1 L; ~
Technology challenges for power, noise and reliability analysis in CPS
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7 j2 M' A0 |& j+ [ |* D7 Z■ 活動時間: 2010年11月30日 星期三 9:00-16:45
# V; V5 y: |* Y U/ y■ 會議場地: 新竹國賓飯店 10樓 宴會廳
8 Z5 {! M, u: U: W■ 洽詢專線: +886-2-8712-8866 分機859 黃先生 " f) e. L6 Q" X: ?
■ 傳真專線: +886-2-8712-0232
3 X' U5 C9 w N, S" p■ 參加方式: 免費活動 (請攜帶名片1張)
( z+ ^8 t( }+ L+ x, ~) j■ 報名方式: 網路、傳真報名 |
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