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Staff Verification Engineer
" o, m* Y: Z3 W2 {& m K0 J) a公 司:one famous IC company `# v% V) n, d F, ^8 v8 P
工作地点:上海+ q7 Q, Y: z: l) J* y3 J
) R6 Y& u/ f, ~, U3 q' h. XQualifications
/ N: q6 ^ M2 ]8 M# tMS in EE/CS/ME.
0 J l& V7 r# kMinimum of five years experience.
. _; A4 r; ~9 u# FAdditional qualifications include: Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills.
H5 p; O. {4 `( UCandidate should be familiar with as System Verilog, VMM/OVM/UVM verification methdology. ; c% a! d4 F! |$ V' F `
Candidate should be familiar with industry standard ASIC design and verification tools and flow.
# x6 b$ E% S6 k" w! b: cGood knowledge ddr protocol and computer system achitecture would be an added advantage. " r2 K+ x" T# O& q) y- V; w$ c; z
Good knowledge of Perl and shell programming would be an added advantage.
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Responsibilities: 5 O) z9 G6 F5 h" |9 v9 ~
-Understanding the expected functionality of designs. 9 p9 g1 p0 z6 M5 w6 r9 Q3 ~0 O8 |+ k
-Developing testing and regression plans. 0 Q) i- a& u& a" B4 t
-Designing and developing verification environment.
$ y4 C) Z% \6 {, w-Running RTL and gate-level simulations/regression.
8 G4 ?% V* r, k } m6 r8 E7 t6 s-Code/functional coverage development, analysis and closure.4 b1 b3 m* Y0 ]8 t- C9 z
+ v0 k7 B" }+ ]6 Q7 I6 lRequirements:
7 V4 h: _% s& Y- A: _3 e8 `Experience & Skill: 5 Years
. E9 L7 j% v1 r5 y5 l; p-Design verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.). ( A5 W) o& [4 e
-Knowledge in ASIC/FPGA design process and verification tools. 5 [/ y, v5 x8 W
-Familiar with design and verification languages (Verilog, System Verilog, SVA etc.).
& [! r# r, t9 S9 d2 {3 T- Scripting and automation skills (tcl, perl, makefile etc) a plus.
8 u: V. N+ R2 g' L" r ~9 q-Familiar with C/C++.
8 a) C0 Y. Y4 x: s-Knowledge of DDR protocol a plus. 3 o5 O7 J% }8 v( \- ?; J" S
-Independent and self-managing. |
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