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Staff Verification Engineer
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. t# p# c6 x8 ]$ J8 J公 司:one famous IC company8 N3 j; D' y. c7 i9 H1 b
工作地点:上海
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Qualifications ( ]$ e/ J$ }& k& p% ]3 f: f
MS in EE/CS/ME.
# A8 d) _& l, S0 W6 O7 |Minimum of five years experience. : T+ d2 ]. x7 J5 r! |$ V
Additional qualifications include: Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills.
" y7 C6 M2 F$ b. y# Y& O( B6 |% kCandidate should be familiar with as System Verilog, VMM/OVM/UVM verification methdology.
7 W1 X( C/ T" `, Z: m- |7 }* hCandidate should be familiar with industry standard ASIC design and verification tools and flow.
* o8 W. D. s/ I F- f0 H$ xGood knowledge ddr protocol and computer system achitecture would be an added advantage.
" x- ]6 G- r- ]3 A% k7 V7 U: OGood knowledge of Perl and shell programming would be an added advantage. 4 l5 |5 u( j# j6 N& I6 `. f
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Responsibilities:
) I/ x& |% e) l ^% p-Understanding the expected functionality of designs.
3 i7 ` o3 P# E-Developing testing and regression plans. a1 R( V( k. B7 y$ H
-Designing and developing verification environment.
6 f6 y8 V3 T, l1 j- i. ?6 g-Running RTL and gate-level simulations/regression. ( x: p: P7 |7 e. ]* S: q
-Code/functional coverage development, analysis and closure.
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Requirements: 6 w- k% g5 M- d) k' s
Experience & Skill: 5 Years ( r/ x. q: Z( y: I
-Design verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).
3 h/ s- R1 v6 r4 a, `2 t1 l-Knowledge in ASIC/FPGA design process and verification tools. 8 o# c: A8 i& i: H7 _2 c* z' o
-Familiar with design and verification languages (Verilog, System Verilog, SVA etc.).
+ [' P6 s" s* `- Scripting and automation skills (tcl, perl, makefile etc) a plus.
+ \. [9 X" C6 N-Familiar with C/C++. ) }, o( q/ h1 D8 N8 k9 z' w
-Knowledge of DDR protocol a plus. 0 g4 G {; Z1 @) A8 V5 ~
-Independent and self-managing. |
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