FPGA verification Engineer most difficult job functions?

ranica

招聘公司：a top 15 semiconductor company
* G( F' K5 b1 v7 K9 Z招聘岗位：Product Engineer
$ O, K: q3 M6 e* V& D9 t工作地点：Beijing
+ o, t9 M  ~1 X6 Q, C, b4 c
岗位描述：
- Design database verification by simulation and on FPGA - Chip function evaluation - Develop test firmware and tools (Hardware and Software) - Develop evaluation board - Cooperate to debug chip issues - Customer support • Assist with customers’ issues • Visit customers and provide on-site support • Build up demo system
3 L6 X, r& ]) Q' \
+ f, d9 l1 E  Z0 w, l! e: P: T职位要求：
- BSEE or above with minimum 3 years communication system experience - Familiar with Verilog. Has digital design experience with Verilog in real project - Minimum 3 years FPGA working experience, including code writing, timing analysis, debug - Familiar with at least one of schematic and PCB layout tools - Excellent English skill will be required. - Strong inter-personal, teamwork and communicational skills

ranica

客户 A famous IC company
! T" ~0 O- Y6 I% U0 m8 `  a地点 Shanghai

1 i# g6 V. y0 Z; D# _/ z职位描述
( p$ O  T7 ^/ E3 E$ dWe are looking for a person to join a design team to execute a state-of-the-art IC design project in the wireless communication field. Candidate must be familiar with digital IC design flow with a proven record of design and verification of a complex design project that led to successful silicon. Proficiency in Verilog is required.

职位要求
! ^/ g% b  p! a% s/ n6 B' v2 z/ Q7 pExperience in the following areas of expertise is desired:
Wireless media access control (MAC) design experience would be highly desirable
Knowledge of TCP/IP and DMA Offload Engine design experience will be a plus
RTL design, verification, and chip integration
) |( {. ~+ u$ q( B" g' R& iExperience in the following is beneficial but not necessary requirement:
Communication systems and RF systems
9 V# U! \- L% A8 |" G8 v5 }Familiarity with wireless communication systems and standards (802.11b/g/n and WiGig)
% p) N- ~  \+ q3 e7 m4 j- nKnowledge of interface protocols such as PCI/PCIe would be a plus
/ i/ m# e0 Z: h9 x/ ?FPGA design flow, testing, and emulation bringup
1 g* U; w7 T( [* l+ k) |
( P7 ~% n6 y1 ?6 E. y2 ^' BOther requirements:
1 g' Z  ~, j9 y* FFamiliar with design and verification languages, EDA tools and ASIC/SOC design methodology
: e- q0 M) a1 l/ JGood script language skill, such as Perl, Tcl and Shell
7 b% y/ o  }( PGood written and oral communication skills in English
Good Team player
+ f, d' v1 K1 A9 j$ k( \. F( @Candidates must have MSEE degree with at least 5 years of experience

ranica

招聘公司：A famous IC company
招聘岗位：高级ASIC设计工程师
9 S9 ?! ~; H3 P" |  F' _工作地点：Shanghai
- Z" `: h* x1 S) @
岗位描述：
* h: G; p3 f+ ?7 _1、定义设计模块结构并编写芯片设计规范； 2、使用VHDL/Verilog编写逻辑模块的RTL代码； 3、编写测试向量对模块进行仿真验证； 4、在FPGA平台上进行芯片级的测试验证； 5、进行模块级的芯片综合与时序分析； 6、编写完整的设计和验证报告。

职位要求：
1、具有电子或通信工程类硕士以上学历； 2、 熟练运用Verilog/VHDL进行芯片前端设计，熟练运用设计仿真综合和测试工具，如quartus，Xilinx，modelsim，nc，debussy，逻辑分析仪，信道仿真设备等； 3、深刻理解数字电路设计和时序分析方法，并拥有故障定位和解决问题的能力； 4、深刻理解通信原理、数字信号处理等基础知识，熟悉无线通信原理与常用算法； 5、具有3年以上芯片设计经验，拥有无线通信物理层开发项目（如DTMB、CMMB、DVB、3G, LTE等）经验者优先； 6、工作认真严谨，积极上进； 7、良好的团队合作意识和沟通能力。

ranica

Verification Engineer
; R, p# C0 c1 T1 s. J* j$ @
公      司：A famous IC company
工作地点：上海

The Role:
·         ASIC  verification
/ C& {3 U: ^( P( V1 [/ o  j·         Work closely with the California teams
' Z8 k& o  x& _7 l1 H0 {5 }& B. r7 N' o·         Support chip tape out and bring up
3 v$ ~1 U& f9 ~& v: U1 A
& Y1 |4 _. \; `9 ~0 s/ d' b4 KRequirements:
·         3+ years experience in ASIC Verification
3 W, U: q8 w& k9 G4 s·         BS in Electrical Engineering (or equivalent) is a must have, MSEE is desired
. i& m4 H- U& n' G" m, O) ?4 x·         System on Chip (SOC) Verification Experience, including AHB/AXI, CPU, Interface integration verification
  c7 z: ~( Y4 ]( ?: `·         Very familiar with verification languages – Verilog, System-Verilog, and VMM
- l! O. i- @; \: V5 M·         Test plan and test case documentation
, j0 n$ a- K5 p6 z  y: P·         Functional coverage and code coverage analysis
7 X- `( Q4 `+ j& c% U·         Must be familiar with various scripting languages used in verification, including Perl, Csh, Make, etc.
·         Experience verifying interfaces such as PCIe, Ethernet, DDR, USB
$ m4 S/ V; f6 c/ I9 T, p·         Working knowledge of networking protocols 802.3 and 802.11, especially Medium Access Control and TCP/IP
* n8 E; l5 P4 ^/ g5 n1 a·         Working knowledge of C programming language
·         Must be familiar with the ASIC verification flow from feature identification to test bench development and through final tape out sign-off
; q6 R% \: o9 Y0 L3 U·         FPGA emulation experience a plus
·         Chip bring-up experience, including use of Logic Analyzer and Oscilloscope for debugging

ranica

ASIC Digital Verification Engineer
" w, {5 M$ i8 c" h9 G公      司：A mobile chipset semiconductor company
/ A1 N1 ^' W% [; g( J% W- J工作地点：上海
7 t: F. [, ~# l
Responsibilities:  
  Make verification plan for one module or whole chip.  
+ J3 s& |5 T0 r' ]  Build up and maintain module-level and chip-level verification environment  
) V. G, G/ r8 o: z  Verify ASIC digital design based on case list, and output verification report.  
  Also responsible for lint checking and formal verification.  
) L: M" P4 l7 V4 }4 l* v
Qualifications:  
9 _# b4 Q, {1 S) l  Proficiency in logic verification.  
  Experience with Verilog logic design language.  
  Experience with high-level verification languages such as System Verilog, System C, Vera or Specman e language.  
  Experience with UNIX/Linux simulation tools such as IUS or VCS.  
  Experience with C and C++ is a plus.  
  Experience with C_SHELL, TCL or PERL is a plus.  
' Q' v' u0 ^9 G- v2 _' M2 T  Experience with UVM, OVM or VMM is a plus.  
1 R- K3 v% D5 P. O, J  Good knowledge of SOC design is a plus.  
  Good knowledge of software design is a plus.  
& Q; i2 q- I. n  Self-motivated and good team player.  
  MSEE or BSEE with 2+ years.

ranica

Senior Digital Design Engineer
$ Q# v" J6 N  d/ T3 v公      司：A leading semiconductor company
工作地点：香港

Job Responsibilities:
    Perform logic design, RTL coding, design verification, logic synthesis, DFT and static timing analysis
    Develop verification environment and coverage closure
! S: P& A# c6 M$ p5 }    Support wafer level testing and silicon evaluation
' e0 ~* ]' y$ s+ K* i    Prepare technical documents

% x4 d. a2 j, G" B, `7 C1 wJob Requirements:
    B.Sc or above in Electronic Engineering or equivalent. Applicants with postgraduate degree would be considered as an advantage
% x9 i' l( s4 C8 S0 C- H' e% r    5 Years or above of solid experience in one or more of the following areas: Verilog-based logic design and synthesis, constrained random    testbench with System Verilog & UVM, assertion based design verification or circuit-level SPICE simulations
    Knowledge of SoC and embedded system.
8 y- e% s4 K: r    Knowledge of scripting languages such as Perl, TCL and Make
    Candidate with less experience will be considered as Digital Design Engineer

ranica

数字IC验证工程师
$ E, B# f' U$ t9 j6 I' m公      司：A famous IC company
- f) f3 {9 N# T- n4 t工作地点：上海
/ _4 _, y& G; f/ P2 H  D
' n1 k% Q/ E- n: x7 f4 Q岗位职责：
: F: K) D. w# K5 x( S! L/ a# E1、负责整个团队验证平台的搭建、维护
$ U+ \2 l3 w7 ]% g6 i* \2、先进验证方法和验证平台的评估、导入
3、各种IP的模块验证，SOC相关的集成验证、系统验证，负责验证计划的制定实施、测试用例的编写。

" B% g& p( n( g! |* X$ q/ X职位要求：
1、大学本科及以上学历，电子、通信、计算机或微电子专业；
+ D; N$ S7 i5 ?2 o: A2、熟练掌握Verilog、SystemVerilog、C/C++等语言的编程，有扎实的数字电路基础；
7 o" i: K6 T7 {  G9 e9 \" i; M! k3、熟悉SoC验证开发流程，了解常用的验证方法学，如VMM等；
+ n# I- h1 O( ?$ z+ V3、有1~2年芯片验证的相关工作经验；
/ O8 T  W8 E  I4、具有较强的学习能力、沟通能力和良好的团队合作精神；
5、有基于ARM处理器的SOC芯片验证经验者优先考虑。

ranica

Senior Digital Design Engineer
公      司：A famous European IC company
% {  J. ^" C$ a1 B8 o: ^% [  e工作地点：上海

7 w  B5 `3 f! A# @Job description  
- define system partitioning of s/c circuits and system  
- P1 h/ E# V! F, u* O" ~- define HW/SW co-partitioning  
. D8 x" g" U/ n" U- provide technical feasibilities based on system simulation and/or FPGA based demonstrator  
- propose new technical solutions on s/c and system level  
- design digital part of mixed signal (smart power) ASICs  
4 X3 y% e. [+ f/ I7 q2 L) K; g/ s- close cooperation and interaction with international teams  
- coach junior engineers  
% X. H+ z9 R* I( j! y" G
Required knowledge competencies and attributes  
' m/ [$ k2 m" u: M1 I, I- master degree in microelectronic circuits or systems, Communications, Computer Engineering (or equivalent)
8 B  j6 i, U- L/ b* P; c- > 5ys experience in digital design  
- good understanding of ASIC mixed signal flow (Cadence based)  
: P+ T! J6 y1 ?1 Y$ b  P- strong background in HDL coding, verification and toplevel integration  
, }! N# g! i) E% F4 X2 w7 o& S- good understanding of communication interfaces used in Automotive (SPI, CAN, LIN, Flexray)  
0 p# `+ ?; C5 \; T- experience in FPGA development  
# B" `7 P1 ?4 G" _5 w8 z5 ]- very good communication skills (written, oral)  
- self motivated and high level of flexibility  
( M1 T; |/ y+ ^9 |7 m6 ^- foreign languages: English, German (not a must)

ranica

ASIC Verification Engineer (WMAC)
' W! c9 p4 j  L; }; g3 y公      司：A famous IC company
工作地点：上海
, q7 ]$ B, `8 V) O& I6 J
, A: D  D$ z2 Z# T/ r/ u  `. @  ^The Role:
        ASIC design and verification
& ]5 }+ {7 B; `+ B$ J. D* o0 J5 m        Work closely with the California teams
" G% H, U' P4 F% [2 f' y        Support chip tape out and bring up
7 e6 M2 v* M2 b, }' I9 |
4 U5 L. K# V- U0 S+ zRequirement:
        8-10 yrs. experience  
        Knowledge of Verilog / System Verilog & Perl
        Has worked on complex project; experience with 802.11 is preferable
        Can work independently - want him to take over MVE
; x- P5 Q4 j; D8 x) Q/ X9 n$ K        Experience in Networking SOC, Ethernet MAC or any other MAC layer protocol experience is plus

ranica

ASIC Digital Verification Engineer
公      司：A mobile chipset semiconductor company
工作地点：上海

+ o1 @2 _0 ?. k% D* T8 dResponsibilities:  
2 n# ]; Q$ Y7 B/ D* S, n. v  Make verification plan for one module or whole chip.  
1 O4 U, o9 S: z7 B4 ]9 R* O  Build up and maintain module-level and chip-level verification environment  
- ?. m+ }+ |. J5 w  Verify ASIC digital design based on case list, and output verification report.  
+ c0 F9 b! h; w" K. {0 p  Also responsible for lint checking and formal verification.  

! Q$ P. f- D( {, K2 oQualifications:  
: e6 F% h. O  b7 H  Proficiency in logic verification.  
  Experience with Verilog logic design language.  
  Experience with high-level verification languages such as System Verilog, System C, Vera or Specman e language.  
  Experience with UNIX/Linux simulation tools such as IUS or VCS.  
  Experience with C and C++ is a plus.  
  Experience with C_SHELL, TCL or PERL is a plus.  
. i0 i3 |; v5 i3 b9 f% g! }  Experience with UVM, OVM or VMM is a plus.  
  Good knowledge of SOC design is a plus.  
* \3 B+ b# q6 H/ f  Good knowledge of software design is a plus.  
, A- R& o) U& a$ @- t& I9 t  Self-motivated and good team player.  
) a6 ~4 u& p: W4 d  MSEE or BSEE with 2+ years.

ranica

Staff Verification Engineer
公      司：one famous IC company
5 t' E, m! c& H2 _, O' e工作地点：上海
9 G4 F5 ]! w/ Q* ~% C
Qualifications
* j( p- L: \0 y. k1 _5 t, PMS in EE/CS/ME.  
Minimum of five  years experience.
: d3 w' `2 w5 aAdditional qualifications include: Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills.
Candidate should be familiar with as System Verilog, VMM/OVM/UVM verification methdology.
Candidate should be familiar with industry standard ASIC design and verification tools and flow.
Good knowledge ddr protocol and computer system achitecture would be an added advantage.
! }- y: I8 [( f+ W2 SGood knowledge of Perl and shell programming would be an added advantage.  
; K# Q: L$ Y0 e9 S$ ~
* o, t6 n! U0 V7 EResponsibilities:
-Understanding the expected functionality of designs.
-Developing testing and regression plans.
3 g1 G5 G) h8 r" H  r6 h-Designing and developing verification environment.
-Running RTL and gate-level simulations/regression.
-Code/functional coverage development, analysis and closure.
4 d1 |. d5 Z  w
Requirements:
, \$ S9 _* U( x7 p& Z/ ?# GExperience & Skill: 5 Years
7 o$ S: c" ~7 m-Design verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).
9 |" L5 R* n" ^5 k8 `-Knowledge in ASIC/FPGA design process and verification tools.
-Familiar with design and verification languages (Verilog, System Verilog, SVA etc.).
- Scripting and automation skills (tcl, perl, makefile etc) a plus.
-Familiar with C/C++.
: @) ~: p2 _, Q-Knowledge of DDR protocol a plus.
+ @; H8 ^$ `/ ?) p# a-Independent and self-managing.

ranica

Staff Verification Engineer
5 V! t# H0 c: L+ p8 e
公      司：one famous IC company
工作地点：上海
7 g" s2 `! X; k3 u1 d% s$ p$ {
Qualifications
MS in EE/CS/ME.  
Minimum of five  years experience.
Additional qualifications include: Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills.
& n+ u0 |% Z+ j) G( R! \! ?4 UCandidate should be familiar with as System Verilog, VMM/OVM/UVM verification methdology.
Candidate should be familiar with industry standard ASIC design and verification tools and flow.
: N# C* G; G& k+ P9 A6 Z& ^2 {Good knowledge ddr protocol and computer system achitecture would be an added advantage.
Good knowledge of Perl and shell programming would be an added advantage.  
' J9 p) G# v+ y) }! k
Responsibilities:
-Understanding the expected functionality of designs.
  h+ [* A0 b3 ~4 B-Developing testing and regression plans.
-Designing and developing verification environment.
-Running RTL and gate-level simulations/regression.
-Code/functional coverage development, analysis and closure.

  L$ i% F" W+ M5 o  Y# oRequirements:
Experience & Skill: 5 Years
9 s8 {; r5 O- q! W5 R-Design verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).
-Knowledge in ASIC/FPGA design process and verification tools.
-Familiar with design and verification languages (Verilog, System Verilog, SVA etc.).
- Scripting and automation skills (tcl, perl, makefile etc) a plus.
* X6 y, Y# W& Y0 a. Z! V4 h, l4 g* t-Familiar with C/C++.
-Knowledge of DDR protocol a plus.
-Independent and self-managing.

ranica

Digital Design Engineer

. J1 U5 |7 g# ^  I* e1 M公      司：A famous IC company
$ w$ P1 C5 [) F9 C+ v  B6 r8 _8 |工作地点：上海
2 U( ^$ ^0 ^+ n6 K1 \
* Y& y2 P* l' J+ C1 S7 ^: R. DDuties
Work with internal and external customers to understand product requirements.
3 o9 l+ |8 N0 R& lCreate critical silicon technologies to meet the product requirements.
Work out critical design flows and methodologies to execute implementation flawlessly.
5 }* I2 \  ~( E$ {  T2 ]- CDesign and deliver final design through multiple stages like specification, micro-architecture, IP  development, RTL coding, verification, logic synthesis, DFT, timing convergence, as well as helping on physical implementation.
Complete full documentation.
4 E; s+ t6 q( }2 o5 THelp and mentor junior engineers.
% P' |' {* o( ~/ C
8 i4 D7 c$ O5 ~+ i- bJob Requirements:  
. r8 O0 M/ y! [1 B% D# LSolid understanding of all SoC chip development stages is required.  
! y: s% K! D* V5 EHands-on Experience with complex SoC design flow is required.  
Hands-on Experience with RTL coding, simulation, verification is required.
Experience with DFT and timing tools is preferred.
Experience with ARM platform is preferred.
7 Y- y0 ?8 ]0 Y! j) |1 `Experience with low power design flow is preferred.
  ]; u& r( Q6 R3 m) b, I$ y+ W4 JExperience with system verilog is preferred.
2 B/ Y8 L$ J2 O0 _& l/ AGood organization and documentation abilities  
! o0 {4 N' O8 CMS in Electrical Engineering and Computer Science with 4 years of experience in SoC design