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發表於 2014-6-20 08:56:35
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Staff Verification Engineer( g- p6 S$ ^ m! _8 A' U9 F
+ Q6 k- j) L; [/ m* L! V* T2 M公 司:one famous IC company
2 {) ?! M& E7 y4 L9 q工作地点:上海
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Qualifications 8 t. X) r6 S7 c
MS in EE/CS/ME. 4 H5 x8 Y3 n4 |2 o; M; c
Minimum of five years experience. 9 A& ^9 T) ~4 e5 f
Additional qualifications include: Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills.
3 W, r& B$ h' sCandidate should be familiar with as System Verilog, VMM/OVM/UVM verification methdology. , D/ q3 \9 O9 C$ Z* ~
Candidate should be familiar with industry standard ASIC design and verification tools and flow.
% [9 i. ^& S: m5 s* Y3 sGood knowledge ddr protocol and computer system achitecture would be an added advantage. + _% p1 ^: o4 q, |5 |
Good knowledge of Perl and shell programming would be an added advantage.
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# j2 Z) W( G1 z9 ~Responsibilities: . l5 c: x5 D% z
-Understanding the expected functionality of designs. " l$ M" V, K& z! b
-Developing testing and regression plans.
( b0 G# e5 T$ r% x-Designing and developing verification environment. ) \# e+ S6 q6 _' a
-Running RTL and gate-level simulations/regression.
) h3 r p4 L5 ]! _' _/ m" S-Code/functional coverage development, analysis and closure.. y# f6 r, [/ N2 D* v5 y1 `
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Requirements: 3 z+ T9 q1 B# m7 D
Experience & Skill: 5 Years * e. y U2 n: D8 w7 i
-Design verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.). ( r. ~ `/ t7 p4 ]. I* D
-Knowledge in ASIC/FPGA design process and verification tools. # c# N1 h3 @9 D" \
-Familiar with design and verification languages (Verilog, System Verilog, SVA etc.).
& a- J3 V( C3 ]# s) C! `+ F- Scripting and automation skills (tcl, perl, makefile etc) a plus. - |$ I2 m1 X+ a' c: i
-Familiar with C/C++.
, E2 j- w7 G9 o: O$ D-Knowledge of DDR protocol a plus.
7 V' K; v; P! ~" G-Independent and self-managing. |
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