FPGA verification Engineer most difficult job functions?

ranica

招聘公司：A fabless IC design company
" @+ J4 R! T* @, f0 M. P招聘岗位：系统产品经理
3 E  {3 ?( O3 K. Y. v工作地点：Beijing
2 |0 @! k! C! O; b# x' H7 u1 ?
岗位描述：
; G* _1 C1 G2 Z# X& J8 [: M3 ^主要职责： 定制芯片的实际应用方案，为客户提供具体系统应用的解决方案，统计芯片在应用中出现的问题并形成改进建议书。
! V6 o# @* S1 G" a  o
职位要求：
职位需求： 1. 计算机、通信、电子工程类专业，本科及以上学历。英语CET-4级以上水平，良好的英文读写能力； 2.了解民用消费类产品的框架结构及应用领域； 3. 具备较强的芯片级理解能力，对高速视频接口（LVDS, DVI, HDMI, DP）、数字电视相关芯片有深入的研究或应用，可以很准确的知道芯片的指标含 义和解释； 4. 熟练掌握 Cadence或PowerPCB/Powerlog ic等软件，熟知原理图设计，PCB 的布线规则和产品的生产流程。能够独立调试系统板级硬件； 5. 具备敏锐和快速的反应能力；良好的思维能力、信息收集、分析能力； 6. 良好的团队合作意识和沟通能力； 7. 适应经常出差，勤奋刻苦，爱岗敬业； 8. 具有较强的嵌入式软件编程能力，熟悉LINUX系统的应用。能够独立调试系统系统软件； 9. 具有产品应用及管理经历者优先。

ranica

招聘公司：A famous IC company
招聘岗位：SoC System Verification Engineer
工作地点：Xi'an

1 f' A: \2 F8 p0 k% ], a' Y- K) p岗位描述：
Job Description: * Defines and develops system validation environment and test suites. * Hardware System Validation of Baseband ICs and peripheral for Mobile Terminals Technical coordination possible depending on experience and skills * Functional verification of the baseband IC and analyze of the occurring problems * Definition and implementation of test cases for the different modules(HW/SW, Low level drivers, Linux drivers) * Lead internal customer support during the evaluation phase * Interface to Concept Engineering Team, Design Team, SW Team

ranica

职位要求：
2 Y, h) O4 j+ A. m! ^' dJob Description: * BS. or MS. Degree, MS. preferred, in Electrical / Electronics Engineering or equivalent * Minimum 2 years experience with the following tools/domains are recommended: * Knowledge of Embedded system * ARM Tools (ADS), GCC know how * Script languages (GNU Make, Make, Make File structures) * Debug Tooling Multi-ICE, Lauterbach, OS-aware debugging * RTOS Symbian, Nucleus, Linux or equivalent * Usage of C models (Virtual Prototype) to test Software before silicon availability * Configuration Management (Versioning Tools: ClearCase) * Knowledge of the following cores/architecture concepts are recommended: * ARM 7/9/11/Cortex Series and all controller functions: Interrupt/DMA... * Multimedia concept: JPEG, MPEG, Camera, Display, Multimedia Card Storage devices... * Standard Interfaces (UART, SSC, I2C, USB HS, USB FS, USB HSIC, MIPI HSl, SlimBus, MIPI Unipro¿) * Memory devices (DDR1, DDR2, SDRAM, Mobile RAM, NAND and NOR Flash) * Connectivity functions: WLAN, BlueTooth, GPS, FMR... * Good English, Excellent communication skill and team spirit oriented

ranica

招聘公司：A famous IC company
8 k/ p6 F0 v6 P. V2 e. e; K招聘岗位：Digital Design Engineer
工作地点：Beijing
8 h2 {% c6 b9 M6 X" f6 J
岗位描述：
Duties · Digital design, including synthesis, timing simulations, power optimization, DFT · Mixed signal design; and verification · Define, develop, and implement characterization, test plans, test vector generation · Work with other division test groups inside/outside FSC to identify possible co-operative opportunities to optimize test solution · Work on the design of analog blocks like voltage regulators, I/O buffer, output drivers, voltage references, oscillators · Work with product definition; characterization, and test engineers in the full product development flow; Work with application & test engineers to define optimal design and characterization solutions, based on design objectives · Layout floor planning, including P&R, DRC, LVS, and LPE

; c- L9 a: \, V/ U& ~职位要求：
Requirements · Minimum 3 years direct digital IC design experience · Minimum 3-5 years direct mixed signal IC design experience · CMOS mixed signal circuit design and proficiency with industry standard design tools and Verilog/VHDL · Knowledge in CMOS/BiCMOS Analog circuit design Experience in Cadence IC Design tool set, simulation, verification · Matlab/Simulink/VerilogA or other behavioral simulation expertise a plus Team-based, cross-functional organizational structure experience preferred · Excellent written and oral communication and presentation skills · Satisfactory written and oral communication skills in English · MSEE degree or above or equivalent experience · Strong communications skills; written, verbal, presentation and listening; · Good interpersonal skills to work in a team environment; · Good command of written and spoken English required; · Excellent interpersonal, written communication and presentation skills

ranica

招聘公司：A famous IC company
; G% o3 A# \0 `- `招聘岗位：Sr. Design Engineer
工作地点：Shanghai、Beijing

- c% i3 S  F( i" K" P7 M岗位描述：
Duties · Analog IC circuit design, simulation and verification · Design analog products and blocks such as high current or high capacitive load output drivers, operational amplifier, comparator, voltage reference, oscillator, error amplifier, voltage regulator etc. · Design of the switching power IC, DC-DC converters, for mobile/portal application · Evaluation, simulation and analysis of power architectures and circuit topologies · IC layout including floor planning, DRC, LVS, and LPE · Work with application and testing engineers to define optimal characterization and testing solution · Work with product definers and product engineers in full product development flow

职位要求：
Requirements · Minimum 5 years direct DC-DC IC design experience, with MSEE or above degree · Strong knowledge in analog CMOS and Bipolar IC design · Working direct experience with switching power supplies, DC-DC converters, Battery charger, and their various topologies · Theoretical understanding of the power electronics, switching power supply topologies · Prior experience with power management related IC design a strong plus · Knowledge in analog IC layout · Matlab/Simulink/VerilogA or other behavioral simulation expertise a plus · Excellent written and oral communication and presentation skills · Satisfactory written and oral communication skills in English · MSEE degree or above or equivalent experience · Strong communications skills; written, verbal, presentation and listening; · Good interpersonal skills to work in a team environment; · Good command of written and spoken English required; · Excellent interpersonal, written communication and presentation skills

ranica

招聘公司：a top 15 semiconductor company
招聘岗位：Product Engineer
& Y. K" j* m+ |3 C( S" C) P7 k工作地点：Beijing

7 C* \+ O0 o; _* J) i' w/ J岗位描述：
( n/ W* O6 @$ O- Design database verification by simulation and on FPGA - Chip function evaluation - Develop test firmware and tools (Hardware and Software) - Develop evaluation board - Cooperate to debug chip issues - Customer support • Assist with customers’ issues • Visit customers and provide on-site support • Build up demo system

职位要求：
1 }  w. G% C  P9 R- b: o% t- BSEE or above with minimum 3 years communication system experience - Familiar with Verilog. Has digital design experience with Verilog in real project - Minimum 3 years FPGA working experience, including code writing, timing analysis, debug - Familiar with at least one of schematic and PCB layout tools - Excellent English skill will be required. - Strong inter-personal, teamwork and communicational skills

ranica

客户 A famous IC company
6 A/ r& q* m( g* R" I: X% j: c地点 Shanghai
/ o' x. k, B# f) c0 I
: b! E7 E) ^5 |, n8 J职位描述
We are looking for a person to join a design team to execute a state-of-the-art IC design project in the wireless communication field. Candidate must be familiar with digital IC design flow with a proven record of design and verification of a complex design project that led to successful silicon. Proficiency in Verilog is required.
6 a- Q" i: k3 |
1 x# x' `0 L  @  H* i9 V+ Z职位要求
5 g7 {9 U4 Y$ y6 s5 Q& e2 V3 BExperience in the following areas of expertise is desired:
% v5 }' }4 ]0 _! g1 T7 o4 |Wireless media access control (MAC) design experience would be highly desirable
Knowledge of TCP/IP and DMA Offload Engine design experience will be a plus
: G# d* E2 K/ v; Q# XRTL design, verification, and chip integration
+ j! ^# w$ M6 Q/ K2 I# Z. DExperience in the following is beneficial but not necessary requirement:
- s4 K( {& I& _+ r1 B- sCommunication systems and RF systems
Familiarity with wireless communication systems and standards (802.11b/g/n and WiGig)
8 C7 g/ i. }% e  EKnowledge of interface protocols such as PCI/PCIe would be a plus
FPGA design flow, testing, and emulation bringup

$ f, e. F; u7 u2 KOther requirements:
, }' N) V5 E5 F2 OFamiliar with design and verification languages, EDA tools and ASIC/SOC design methodology
Good script language skill, such as Perl, Tcl and Shell
% J& N* e, ]8 O; T) O7 S5 v4 ]Good written and oral communication skills in English
Good Team player
% P) C! m* P( S  o5 W2 W1 oCandidates must have MSEE degree with at least 5 years of experience

ranica

招聘公司：A famous IC company
8 g. t1 L( p, i! b, H0 N0 e  W招聘岗位：高级ASIC设计工程师
0 c( C  [( \& O" b工作地点：Shanghai

2 S" I7 F$ c5 S) S% d) b; N5 E岗位描述：
1、定义设计模块结构并编写芯片设计规范； 2、使用VHDL/Verilog编写逻辑模块的RTL代码； 3、编写测试向量对模块进行仿真验证； 4、在FPGA平台上进行芯片级的测试验证； 5、进行模块级的芯片综合与时序分析； 6、编写完整的设计和验证报告。
: {# r* w1 Z% ]8 G2 t; y
职位要求：
1、具有电子或通信工程类硕士以上学历； 2、 熟练运用Verilog/VHDL进行芯片前端设计，熟练运用设计仿真综合和测试工具，如quartus，Xilinx，modelsim，nc，debussy，逻辑分析仪，信道仿真设备等； 3、深刻理解数字电路设计和时序分析方法，并拥有故障定位和解决问题的能力； 4、深刻理解通信原理、数字信号处理等基础知识，熟悉无线通信原理与常用算法； 5、具有3年以上芯片设计经验，拥有无线通信物理层开发项目（如DTMB、CMMB、DVB、3G, LTE等）经验者优先； 6、工作认真严谨，积极上进； 7、良好的团队合作意识和沟通能力。

ranica

Verification Engineer
9 T6 }# n; r7 y) x  C, i
$ `  ^, w, o) u- m# P5 q公      司：A famous IC company
工作地点：上海
# f' l7 E3 }. a8 t+ V
The Role:
/ Z6 _* o3 g1 f1 |: I% g4 |·         ASIC  verification
·         Work closely with the California teams
·         Support chip tape out and bring up
( P; @7 a8 U' @& b
% `8 A1 v& X( m7 q8 w9 o# FRequirements:
( l. u& \- {& p8 j: V·         3+ years experience in ASIC Verification
·         BS in Electrical Engineering (or equivalent) is a must have, MSEE is desired
  }% S' ?+ S5 e9 Z3 ]$ q7 @·         System on Chip (SOC) Verification Experience, including AHB/AXI, CPU, Interface integration verification
·         Very familiar with verification languages – Verilog, System-Verilog, and VMM
) E2 h: g; c+ L/ l( }% e& z8 K·         Test plan and test case documentation
) ^$ a9 f4 {1 r( Q' y/ ]·         Functional coverage and code coverage analysis
' }5 K. k( Z: w. u5 h·         Must be familiar with various scripting languages used in verification, including Perl, Csh, Make, etc.
/ g! @% A# k6 H) M) F; \·         Experience verifying interfaces such as PCIe, Ethernet, DDR, USB
·         Working knowledge of networking protocols 802.3 and 802.11, especially Medium Access Control and TCP/IP
" D3 g, s8 k7 i- a0 f·         Working knowledge of C programming language
0 ~* {+ `6 d5 `! Z4 s3 s·         Must be familiar with the ASIC verification flow from feature identification to test bench development and through final tape out sign-off
·         FPGA emulation experience a plus
·         Chip bring-up experience, including use of Logic Analyzer and Oscilloscope for debugging

ranica

ASIC Digital Verification Engineer
( @  t5 b7 S  D7 t$ b& s5 z3 g公      司：A mobile chipset semiconductor company
工作地点：上海

Responsibilities:  
  Make verification plan for one module or whole chip.  
3 q4 ]6 w# M. [1 G" S  Build up and maintain module-level and chip-level verification environment  
  Verify ASIC digital design based on case list, and output verification report.  
+ b" X. R0 v) f  }/ ?4 S( g) N3 I  Also responsible for lint checking and formal verification.  

9 T# g: ^9 w3 ^  IQualifications:  
  Proficiency in logic verification.  
; D" }3 ?; n7 z. D9 e/ G5 j  Experience with Verilog logic design language.  
  Experience with high-level verification languages such as System Verilog, System C, Vera or Specman e language.  
: J$ ?/ e, R9 {$ k0 _  {* C  Experience with UNIX/Linux simulation tools such as IUS or VCS.  
; l1 Y( o( |. R3 ^9 o/ A& L, v) m  Experience with C and C++ is a plus.  
  Experience with C_SHELL, TCL or PERL is a plus.  
  Experience with UVM, OVM or VMM is a plus.  
  Good knowledge of SOC design is a plus.  
  Good knowledge of software design is a plus.  
  Self-motivated and good team player.  
. M7 r- k1 W/ }7 O/ x6 s  MSEE or BSEE with 2+ years.

tk02561

Hardware Applications Engineer–Graphics
公      司：A famous IC company
工作地点：上海

Desirable
Strong understanding of microprocessors
A good understanding of the interaction between software and hardware
: P5 S2 [4 C# q/ P1 eUnderstanding of FPGA or ASIC implementation flows (synthesis, scan insertion, layout)
; R6 R0 W7 Y/ B9 i  fC/C++, assembler coding or other programming skills.
/ l( E8 O( e4 s* o, o( ?Knowledge of GPU or graphics processing specification, like OpenGLES, Direct-X, is preferred
5 d, S# n- m* o8 H' ?' B. S6 v/ Q
+ V% Q8 e2 |% V! X$ S; X! \Job Requirements：

tk02561

Education
) I4 H% V* {5 _; bGood university degree, in Computer Science or Electronics Engineering ideally, although other science graduates would be considered if they have relevant experience.
  
" B$ ~9 t+ Y7 JExperience
. ]9 g7 y) ^! E* BMinimum of 4 years industrial experience
0 N2 S2 ^8 o) B' H6 V& xExperience or knowledge of FPGA or ASIC design, simulation and/or verification techniques, including RTL coding and simulation, in Verilog or VHDL
0 U2 A$ g0 |( p+ mExperience in integrating SoC peripherals
Experience of interacting with colleagues outside of China
- v% X! L# q& u' kProfessional experience of customer and sales interaction
Demonstrable experience of problem solving and debug skills

Personal Requirements
$ g) L/ H$ V- G& n* {2 K# ]Must have excellent written and verbal communication skills with both colleagues and customers, including good written and spoken English
6 Y5 {' b1 Z! C: KMust be proactive in obtaining engineering or management input, in order to complete project and internal tasks in a timely and accurate manner
Must have the desire and ability to solve problems quickly
Must be enthusiastic and well driven
# q+ `& {0 J3 v/ ^' \& WMust be able to schedule own workload and plan tasks – based on both internal and customer requirements.  
Must have good inter-personal skills, and be able to work well within a team; especially when under pressure
. b9 U  K0 T0 ]3 gMust be willing to be flexible and accept new challenges
" s1 u# N( ^8 B5 g: G: ^Must be able to travel on a regular basis, both to give customer training and also for internal business reasons.

ranica

Senior Digital Design Engineer
公      司：A leading semiconductor company
工作地点：香港

, j4 Y/ f1 A- n4 ^; MJob Responsibilities:
# P7 g% `) Z, o    Perform logic design, RTL coding, design verification, logic synthesis, DFT and static timing analysis
    Develop verification environment and coverage closure
4 y& P  m5 ~& T    Support wafer level testing and silicon evaluation
    Prepare technical documents

Job Requirements:
; p1 t. C6 |% n' w+ F! J    B.Sc or above in Electronic Engineering or equivalent. Applicants with postgraduate degree would be considered as an advantage
    5 Years or above of solid experience in one or more of the following areas: Verilog-based logic design and synthesis, constrained random    testbench with System Verilog & UVM, assertion based design verification or circuit-level SPICE simulations
    Knowledge of SoC and embedded system.
: A4 v. y* N& v" q$ B. q    Knowledge of scripting languages such as Perl, TCL and Make
( E" g- S/ D, d. U/ E    Candidate with less experience will be considered as Digital Design Engineer

ranica

数字IC验证工程师
1 J% _1 H) q* Y* k公      司：A famous IC company
; _6 i8 x5 Z( X& C工作地点：上海

9 H4 d1 v: U/ N: L+ w- B岗位职责：
# N4 U& G. N6 t% F1 E( D' I4 m1、负责整个团队验证平台的搭建、维护
% \7 R" t2 [6 o4 m" }2、先进验证方法和验证平台的评估、导入
" Q/ g8 p6 {- E, c$ m" f+ Q9 z' P/ q3、各种IP的模块验证，SOC相关的集成验证、系统验证，负责验证计划的制定实施、测试用例的编写。
8 H, W, N6 R1 O4 \3 u: t
* ~( ]& i+ _3 k' B职位要求：
1、大学本科及以上学历，电子、通信、计算机或微电子专业；
4 ~4 V. @; {# V5 D" `2 Y1 [7 i2、熟练掌握Verilog、SystemVerilog、C/C++等语言的编程，有扎实的数字电路基础；
. i& m! f* @2 T- q; ]3、熟悉SoC验证开发流程，了解常用的验证方法学，如VMM等；
# Q& {( m2 n: b2 B$ k$ I3、有1~2年芯片验证的相关工作经验；
4、具有较强的学习能力、沟通能力和良好的团队合作精神；
5、有基于ARM处理器的SOC芯片验证经验者优先考虑。

jcase

数字IC验证工程师
$ y4 v/ S+ q6 T: R公      司：A famous IC company
5 C: \' y( l" ]( ]$ Q! U* S/ b工作地点：上海

岗位职责：
1、负责整个团队验证平台的搭建、维护
9 W  B! X$ O# W2、先进验证方法和验证平台的评估、导入
3、各种IP的模块验证，SOC相关的集成验证、系统验证，负责验证计划的制定实施、测试用例的编写。

% d! B% s: v& U: G9 L职位要求：
1、大学本科及以上学历，电子、通信、计算机或微电子专业；
* \# M7 z; Y4 k, k3 S2、熟练掌握Verilog、SystemVerilog、C/C++等语言的编程，有扎实的数字电路基础；
3 p& ?  Q. A0 H, n# ^; P( w3、熟悉SoC验证开发流程，了解常用的验证方法学，如VMM等；
3、有1~2年芯片验证的相关工作经验；
7 O/ k2 C: @' a% P$ x$ ?4、具有较强的学习能力、沟通能力和良好的团队合作精神；
& `. Z; d  ]  S7 S5、有基于ARM处理器的SOC芯片验证经验者优先考虑。

ranica

Senior Digital Design Engineer
公      司：A famous European IC company
工作地点：上海

Job description  
0 i8 F$ O5 A; n. O: G' d" u- define system partitioning of s/c circuits and system  
- define HW/SW co-partitioning  
- provide technical feasibilities based on system simulation and/or FPGA based demonstrator  
2 p, J; x9 }. ^# Y6 \/ r- propose new technical solutions on s/c and system level  
" ^% C. y4 |* `2 y. o- design digital part of mixed signal (smart power) ASICs  
- close cooperation and interaction with international teams  
- coach junior engineers  

Required knowledge competencies and attributes  
. Y1 |" @3 }* y2 n4 e- C+ I2 D- master degree in microelectronic circuits or systems, Communications, Computer Engineering (or equivalent)
- > 5ys experience in digital design  
- good understanding of ASIC mixed signal flow (Cadence based)  
- strong background in HDL coding, verification and toplevel integration  
- good understanding of communication interfaces used in Automotive (SPI, CAN, LIN, Flexray)  
, ~+ g6 Y% h3 ]' I  B4 m# |& t2 A+ P  P- experience in FPGA development  
7 f6 b" Z: b% ^" q% f- very good communication skills (written, oral)  
- self motivated and high level of flexibility  
- foreign languages: English, German (not a must)

sophiew

数字IC验证工程师
, |) z7 d3 y& N. z0 U$ c公      司：A famous IC company
: ?  Q$ N8 f# O8 H' J3 C工作地点：上海

岗位职责：
4 h' X4 J8 R9 \2 A1、负责整个团队验证平台的搭建、维护
: y1 I5 C4 }' t' v1 s5 z7 F3 a& M2、先进验证方法和验证平台的评估、导入
# T8 k# J8 v' g7 H3、各种IP的模块验证，SOC相关的集成验证、系统验证，负责验证计划的制定实施、测试用例的编写。

5 e. f2 y) H! s" I) G) w职位要求：
: R% d5 n" `" l0 {3 A: Y/ E1、大学本科及以上学历，电子、通信、计算机或微电子专业；
- F: H9 b; j0 D- V$ z# x: a% H$ G2、熟练掌握Verilog、SystemVerilog、C/C++等语言的编程，有扎实的数字电路基础；
% }* Y9 C5 z7 P5 P# B3、熟悉SoC验证开发流程，了解常用的验证方法学，如VMM等；
1 z# B4 y8 }% S' t+ [3、有1~2年芯片验证的相关工作经验；
/ W) d2 F* |! t2 x( ]: {4、具有较强的学习能力、沟通能力和良好的团队合作精神；
+ H9 W! U) Y' ]5、有基于ARM处理器的SOC芯片验证经验者优先考虑。

ranica

ASIC Verification Engineer (WMAC)
公      司：A famous IC company
' Q  t; T3 z) b0 q7 t- O5 j工作地点：上海

The Role:
- _! ]. l7 A  J0 U$ l- x        ASIC design and verification
; d2 m/ g9 h/ p! p1 l9 S  N. `# g        Work closely with the California teams
" b& ]7 t! C" n0 q' I/ e1 y6 J        Support chip tape out and bring up
  m. ~" O7 A, s$ W% [7 ?& T
Requirement:
6 v& O5 K! t' x! @        8-10 yrs. experience  
        Knowledge of Verilog / System Verilog & Perl
5 S2 v5 {* x6 O& H$ s) S        Has worked on complex project; experience with 802.11 is preferable
, O2 `& W* v4 Z1 L0 z; X1 v        Can work independently - want him to take over MVE
9 W" F  y: ~8 h- C8 T  |        Experience in Networking SOC, Ethernet MAC or any other MAC layer protocol experience is plus

ranica

ASIC Digital Verification Engineer
公      司：A mobile chipset semiconductor company
% X2 }. u# ?: \2 `工作地点：上海
1 r1 r7 t, S( L- p; d1 W- p' V# b
Responsibilities:  
  Make verification plan for one module or whole chip.  
  Build up and maintain module-level and chip-level verification environment  
" \  @8 q( n( Q  D. L9 S/ I3 K  Verify ASIC digital design based on case list, and output verification report.  
! U8 ~  K' i$ i8 s  Also responsible for lint checking and formal verification.  
1 U) P  V/ Q" t7 T" A7 F0 d4 v/ |
* K" y% P/ E" LQualifications:  
3 \3 r) G3 N  q3 h6 ]1 ~  Proficiency in logic verification.  
  Experience with Verilog logic design language.  
- b5 h# `& Y- j% o6 T  Experience with high-level verification languages such as System Verilog, System C, Vera or Specman e language.  
" x( l8 B6 M; l  Experience with UNIX/Linux simulation tools such as IUS or VCS.  
  Experience with C and C++ is a plus.  
  Experience with C_SHELL, TCL or PERL is a plus.  
  Experience with UVM, OVM or VMM is a plus.  
- l/ E1 k7 U2 N  Good knowledge of SOC design is a plus.  
  Good knowledge of software design is a plus.  
  Self-motivated and good team player.  
9 R' {& U6 q" S/ K  MSEE or BSEE with 2+ years.

ranica

Staff Verification Engineer
公      司：one famous IC company
工作地点：上海
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8 A( f3 I0 w3 ~: E, s7 T: ~& A9 hQualifications
3 V2 z  B) L* b7 i. SMS in EE/CS/ME.  
Minimum of five  years experience.
Additional qualifications include: Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills.
Candidate should be familiar with as System Verilog, VMM/OVM/UVM verification methdology.
( l7 G* J! E1 j/ n  V& hCandidate should be familiar with industry standard ASIC design and verification tools and flow.
3 ]" n# `2 `7 z, J8 W" t4 H7 KGood knowledge ddr protocol and computer system achitecture would be an added advantage.
2 \9 m( Z% e3 V  }, x) {# xGood knowledge of Perl and shell programming would be an added advantage.  
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$ a8 y/ @* v: r( U+ SResponsibilities:
, W9 U- U$ D! ]- t% i" Q* [$ M- _-Understanding the expected functionality of designs.
-Developing testing and regression plans.
: n$ [; ^- N5 _! \7 l- D-Designing and developing verification environment.
-Running RTL and gate-level simulations/regression.
& _- ~5 N! x$ T' L-Code/functional coverage development, analysis and closure.
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9 t: P+ b3 O" y' ?& WRequirements:
5 G, X& d3 U7 l- G, b! ~Experience & Skill: 5 Years
-Design verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).
-Knowledge in ASIC/FPGA design process and verification tools.
, r/ \4 y$ S6 E7 J5 b; g4 [; ~-Familiar with design and verification languages (Verilog, System Verilog, SVA etc.).
! B  P- [' |! H" X( N7 O* R- Scripting and automation skills (tcl, perl, makefile etc) a plus.
; N8 W3 @; k5 g+ A, j+ ?# T7 T5 o-Familiar with C/C++.
-Knowledge of DDR protocol a plus.
-Independent and self-managing.