|
Staff Verification Engineer
5 \2 Z H2 o6 r' q3 ^+ p& L: }0 U& |4 }, A3 F; w' V+ M1 ]. B
公 司:one famous IC company0 W4 B2 W+ l! o. k/ p+ w
工作地点:上海
1 o' F9 P9 ~6 B! T J" j9 T* @' v$ [
Qualifications - p1 P2 n) ^' O" o- u9 U; c$ c
MS in EE/CS/ME.
+ D u) }. f, [& @8 uMinimum of five years experience. 2 O2 T8 B+ |+ H! J$ h
Additional qualifications include: Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills.
3 ^6 g3 O3 p& c; M- ^, r: {. cCandidate should be familiar with as System Verilog, VMM/OVM/UVM verification methdology.
- y: b: w: A& S: KCandidate should be familiar with industry standard ASIC design and verification tools and flow.
3 V2 C' q) z7 _6 qGood knowledge ddr protocol and computer system achitecture would be an added advantage. . Z) J; u5 q, N& S" B n9 {( Y( ?
Good knowledge of Perl and shell programming would be an added advantage. " L+ [. Q8 M* g
$ r# I* ^# K9 n& J; k q: U, @Responsibilities:
% V4 G5 Q( s5 r( z8 C-Understanding the expected functionality of designs.
1 \6 ^8 z- R0 H8 K-Developing testing and regression plans.
! L+ q/ U9 n' T, j-Designing and developing verification environment.
- v& R4 A) M" `* ?! K; ^-Running RTL and gate-level simulations/regression. + Z3 X( @% |! ?* ~
-Code/functional coverage development, analysis and closure.
5 V( E$ y% A: U7 l$ d" d6 R* h4 S2 w( Z- a" f0 ]
Requirements:
7 C# ^, Q! a, f6 G: A1 cExperience & Skill: 5 Years m! z' _7 b% O$ u$ ]/ O3 d9 q8 K; ~; i
-Design verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.). 2 g% |6 v" O: g4 x2 U5 M! i
-Knowledge in ASIC/FPGA design process and verification tools. 9 O4 X7 x' R6 z8 I
-Familiar with design and verification languages (Verilog, System Verilog, SVA etc.).
$ r% v8 x* r8 P: q3 ^2 V4 s* N6 T( p* s- Scripting and automation skills (tcl, perl, makefile etc) a plus. q4 r# [) h8 g; d1 p
-Familiar with C/C++. + C+ Z3 e4 s M7 o- L8 \) E& H
-Knowledge of DDR protocol a plus. ) G5 G# U- ~8 c+ |
-Independent and self-managing. |
|