FPGA verification Engineer most difficult job functions?

ranica

Staff Verification Engineer

公      司：one famous IC company
4 u5 p) Z3 a8 a2 w5 e; _5 G工作地点：上海

3 ^% C  k/ h4 g9 F7 {" `0 xQualifications
2 x1 o* c+ |- r6 X) b/ H) vMS in EE/CS/ME.  
2 p  W8 p) K* i) }8 LMinimum of five  years experience.
9 N$ j! D% p5 A# d( n- k- PAdditional qualifications include: Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills.
+ i' H. f) r  c7 g+ V5 q. }Candidate should be familiar with as System Verilog, VMM/OVM/UVM verification methdology.
Candidate should be familiar with industry standard ASIC design and verification tools and flow.
2 b! d% ]; k! I! `! HGood knowledge ddr protocol and computer system achitecture would be an added advantage.
5 \* l0 d. s$ {4 R7 N+ P4 w" fGood knowledge of Perl and shell programming would be an added advantage.  

Responsibilities:
3 k& i6 K$ q  o  Q3 M- n-Understanding the expected functionality of designs.
-Developing testing and regression plans.
-Designing and developing verification environment.
4 F9 G4 t9 R+ {5 I-Running RTL and gate-level simulations/regression.
! E7 p- P& u, x! e  F-Code/functional coverage development, analysis and closure.

Requirements:
1 }1 r8 N! I" S3 w  E1 tExperience & Skill: 5 Years
-Design verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).
-Knowledge in ASIC/FPGA design process and verification tools.
-Familiar with design and verification languages (Verilog, System Verilog, SVA etc.).
- Scripting and automation skills (tcl, perl, makefile etc) a plus.
0 E, s: W$ t3 K9 g-Familiar with C/C++.
-Knowledge of DDR protocol a plus.
-Independent and self-managing.

ranica

Digital Design Engineer
/ L; R/ K1 ]0 B/ c3 k% i5 {0 I
公      司：A famous IC company
工作地点：上海
9 y" {' J4 A2 P$ L- k/ S
% ^* E5 ?: ?) `0 [; r# I) q  aDuties
/ s# o8 H9 {4 V' RWork with internal and external customers to understand product requirements.
  e' w9 T. u/ J1 o) _Create critical silicon technologies to meet the product requirements.
' S, f, V1 @' e' b% I' e) }9 h/ j  zWork out critical design flows and methodologies to execute implementation flawlessly.
Design and deliver final design through multiple stages like specification, micro-architecture, IP  development, RTL coding, verification, logic synthesis, DFT, timing convergence, as well as helping on physical implementation.
" b6 @# A! W2 T5 d& e; DComplete full documentation.
Help and mentor junior engineers.
  e' o' l( }2 F* z+ m! B9 s7 Y' B
Job Requirements:  
  D2 T4 a+ x7 K9 uSolid understanding of all SoC chip development stages is required.  
Hands-on Experience with complex SoC design flow is required.  
Hands-on Experience with RTL coding, simulation, verification is required.
Experience with DFT and timing tools is preferred.
Experience with ARM platform is preferred.
9 J, |8 m+ K/ ^' \. V9 IExperience with low power design flow is preferred.
Experience with system verilog is preferred.
Good organization and documentation abilities  
; z. a+ u9 D, oMS in Electrical Engineering and Computer Science with 4 years of experience in SoC design

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