FPGA verification Engineer most difficult job functions?

ranica

Staff Verification Engineer

公      司：one famous IC company
工作地点：上海

Qualifications
9 s& w4 E. U: e# E5 T- {MS in EE/CS/ME.  
Minimum of five  years experience.
Additional qualifications include: Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills.
Candidate should be familiar with as System Verilog, VMM/OVM/UVM verification methdology.
Candidate should be familiar with industry standard ASIC design and verification tools and flow.
Good knowledge ddr protocol and computer system achitecture would be an added advantage.
) I' I4 s% _% w5 |+ jGood knowledge of Perl and shell programming would be an added advantage.  

% Y1 [# r9 ~4 m8 K3 ]Responsibilities:
-Understanding the expected functionality of designs.
-Developing testing and regression plans.
-Designing and developing verification environment.
-Running RTL and gate-level simulations/regression.
  r% i6 L/ V, i; f! [/ ]-Code/functional coverage development, analysis and closure.

Requirements:
9 ^( B' q7 t/ ~7 f; W: P) DExperience & Skill: 5 Years
-Design verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).
-Knowledge in ASIC/FPGA design process and verification tools.
-Familiar with design and verification languages (Verilog, System Verilog, SVA etc.).
& ~. @+ c8 n% o# k8 G4 Q- Scripting and automation skills (tcl, perl, makefile etc) a plus.
-Familiar with C/C++.
-Knowledge of DDR protocol a plus.
-Independent and self-managing.

ranica

Digital Design Engineer
  E# c) Q* ?  E2 g
& k. q) q+ S, c5 ?% @! Z公      司：A famous IC company
" }! S* X4 [" W工作地点：上海

Duties
Work with internal and external customers to understand product requirements.
Create critical silicon technologies to meet the product requirements.
, H" \& b; \5 y# N! d4 m8 a& t6 FWork out critical design flows and methodologies to execute implementation flawlessly.
7 r8 y8 \) _2 HDesign and deliver final design through multiple stages like specification, micro-architecture, IP  development, RTL coding, verification, logic synthesis, DFT, timing convergence, as well as helping on physical implementation.
$ L% r: R) s% P7 C1 x: fComplete full documentation.
6 e  O# O9 t6 V0 B/ b, v9 Y6 p3 aHelp and mentor junior engineers.

4 u( N/ O6 v' oJob Requirements:  
Solid understanding of all SoC chip development stages is required.  
Hands-on Experience with complex SoC design flow is required.  
Hands-on Experience with RTL coding, simulation, verification is required.
Experience with DFT and timing tools is preferred.
Experience with ARM platform is preferred.
. n3 l/ t5 S8 s) m* O, Z2 _1 {Experience with low power design flow is preferred.
" x4 n4 s% K8 h) n+ M+ ^Experience with system verilog is preferred.
Good organization and documentation abilities  
MS in Electrical Engineering and Computer Science with 4 years of experience in SoC design

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