Circuit and Layout Co-Design for ESD Protection in BCD

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Circuit and Layout Co-Design for ESD Protection in Bipolar-CMOS-DMOS (BCD) High-Voltage Process

Wen-Yi Chen, Student Member, IEEE, and Ming-Dou Ker, Fellow, IEEE
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Abstract—The n-channel lateral double-diffused metal–oxide–
8 t! [$ P. H% @semiconductor (nLDMOS) devices in high-voltage (HV) technologies
* p# }+ q9 R6 d+ a$ f' Nare known to have poor electrostatic discharge (ESD)
robustness. To improve the ESD robustness of nLDMOS, a co-design
method combining a new waffle layout structure and a trigger
circuit is proposed to fulfill the body current injection technique
in this work. The proposed layout and circuit co-design method
, H5 p/ K9 C8 h6 R+ Oon HV nLDMOS has successfully been verified in a 0.5- m 16-V
bipolar-CMOS-DMOS (BCD) process and a 0.35- m 24-V BCD
process without using additional process modification. Experimental
$ t4 P) W+ J' V2 E6 Xresults through transmission line pulse measurement
8 }2 C& }% \+ Z# P- k% a+ l" tand failure analyses have shown that the proposed body current
& E! v; n' i+ z, sinjection technique can significantly improve the ESD robustness
of HV nLDMOS.
6 I$ Z3 }. J/ }$ S2 h
% _6 |8 x0 e7 }# v) cIndex Terms—Bipolar-CMOS-DMOS (BCD) process, body
current injection, electrostatic discharge (ESD), lateral double-diffused
metal–oxide–semiconductor (LDMOS).