Circuit and Layout Co-Design for ESD Protection in BCD

semico_ljj

Circuit and Layout Co-Design for ESD Protection in Bipolar-CMOS-DMOS (BCD) High-Voltage Process

Wen-Yi Chen, Student Member, IEEE, and Ming-Dou Ker, Fellow, IEEE
/ f( w0 E1 s7 ^: w) [
Abstract—The n-channel lateral double-diffused metal–oxide–
& t- M1 k5 Q: O9 ]semiconductor (nLDMOS) devices in high-voltage (HV) technologies
6 ?( g1 n+ w) `are known to have poor electrostatic discharge (ESD)
0 Y& p8 k( j& `& J/ grobustness. To improve the ESD robustness of nLDMOS, a co-design
method combining a new waffle layout structure and a trigger
- q* N' u0 p6 J; X4 k& Ucircuit is proposed to fulfill the body current injection technique
" [0 ~( G/ E4 I3 ?in this work. The proposed layout and circuit co-design method
/ ?/ K! u- f! `& f: ?+ k1 Zon HV nLDMOS has successfully been verified in a 0.5- m 16-V
bipolar-CMOS-DMOS (BCD) process and a 0.35- m 24-V BCD
process without using additional process modification. Experimental
results through transmission line pulse measurement
5 S2 H( X- J' K4 H; t/ |and failure analyses have shown that the proposed body current
& t1 W& D* h, ~3 |injection technique can significantly improve the ESD robustness
of HV nLDMOS.
  G/ Z; q. X: O
Index Terms—Bipolar-CMOS-DMOS (BCD) process, body
current injection, electrostatic discharge (ESD), lateral double-diffused
metal–oxide–semiconductor (LDMOS).

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