Circuit and Layout Co-Design for ESD Protection in BCD

semico_ljj

Circuit and Layout Co-Design for ESD Protection in Bipolar-CMOS-DMOS (BCD) High-Voltage Process

" M. l& b( Z' ^5 `; S. XWen-Yi Chen, Student Member, IEEE, and Ming-Dou Ker, Fellow, IEEE

Abstract—The n-channel lateral double-diffused metal–oxide–
semiconductor (nLDMOS) devices in high-voltage (HV) technologies
/ v2 c7 Y# v* U' R1 t  Tare known to have poor electrostatic discharge (ESD)
robustness. To improve the ESD robustness of nLDMOS, a co-design
method combining a new waffle layout structure and a trigger
7 k6 [% u# ~- s0 Ucircuit is proposed to fulfill the body current injection technique
in this work. The proposed layout and circuit co-design method
6 p+ a" [# m3 t8 T. O9 \on HV nLDMOS has successfully been verified in a 0.5- m 16-V
bipolar-CMOS-DMOS (BCD) process and a 0.35- m 24-V BCD
: n! {1 m  D5 H: hprocess without using additional process modification. Experimental
# k: f  @6 i6 Eresults through transmission line pulse measurement
and failure analyses have shown that the proposed body current
injection technique can significantly improve the ESD robustness
4 A$ O% n  r4 x5 @+ a' K( b; a- qof HV nLDMOS.
; n0 g' S% {6 b. T8 e9 V# j
Index Terms—Bipolar-CMOS-DMOS (BCD) process, body
current injection, electrostatic discharge (ESD), lateral double-diffused
metal–oxide–semiconductor (LDMOS).

xp212125o

看起來有幫助
/ d) @0 O$ T2 e" }- s* L感謝分享
: W! c. ~2 ~" A6 n2 Z4 u先下載來看看
thank you ~