Circuit and Layout Co-Design for ESD Protection in BCD

semico_ljj

Circuit and Layout Co-Design for ESD Protection in Bipolar-CMOS-DMOS (BCD) High-Voltage Process

1 j* Z: S) b1 C! a0 S' l0 VWen-Yi Chen, Student Member, IEEE, and Ming-Dou Ker, Fellow, IEEE
4 ]- `+ z  R$ {: J
& U( g. R, M3 eAbstract—The n-channel lateral double-diffused metal–oxide–
semiconductor (nLDMOS) devices in high-voltage (HV) technologies
2 V6 }- {! ?7 p2 m7 @7 oare known to have poor electrostatic discharge (ESD)
robustness. To improve the ESD robustness of nLDMOS, a co-design
1 S+ v3 @; }1 r# ^$ B4 I$ ~2 lmethod combining a new waffle layout structure and a trigger
circuit is proposed to fulfill the body current injection technique
& [6 L, l( ?9 U" r* S; U! xin this work. The proposed layout and circuit co-design method
( r: n, W% y( |+ ^8 p0 eon HV nLDMOS has successfully been verified in a 0.5- m 16-V
6 O7 [3 ]( A2 |1 g" S/ ?bipolar-CMOS-DMOS (BCD) process and a 0.35- m 24-V BCD
process without using additional process modification. Experimental
4 I, D- x6 y8 o9 L& Mresults through transmission line pulse measurement
/ o" [2 }& ?% \3 k; nand failure analyses have shown that the proposed body current
  \+ p% [4 C# o5 u" R! r* minjection technique can significantly improve the ESD robustness
of HV nLDMOS.
7 F- t+ r0 i5 ?2 ^7 ~* y
Index Terms—Bipolar-CMOS-DMOS (BCD) process, body
current injection, electrostatic discharge (ESD), lateral double-diffused
metal–oxide–semiconductor (LDMOS).

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