Circuit and Layout Co-Design for ESD Protection in BCD

semico_ljj

Circuit and Layout Co-Design for ESD Protection in Bipolar-CMOS-DMOS (BCD) High-Voltage Process
, l1 G% ], P/ I; G0 N
' d7 u' B* a& V( x  h1 ^3 w. ~Wen-Yi Chen, Student Member, IEEE, and Ming-Dou Ker, Fellow, IEEE

Abstract—The n-channel lateral double-diffused metal–oxide–
semiconductor (nLDMOS) devices in high-voltage (HV) technologies
7 [0 Q' H& U, g5 V& dare known to have poor electrostatic discharge (ESD)
robustness. To improve the ESD robustness of nLDMOS, a co-design
: q/ X5 B) O0 j+ t* ^; Mmethod combining a new waffle layout structure and a trigger
8 E4 Y5 q% N4 C3 l7 h' Pcircuit is proposed to fulfill the body current injection technique
in this work. The proposed layout and circuit co-design method
on HV nLDMOS has successfully been verified in a 0.5- m 16-V
  Y  G; d" q! |% N' W# Lbipolar-CMOS-DMOS (BCD) process and a 0.35- m 24-V BCD
process without using additional process modification. Experimental
) `$ l2 @. i6 S( [results through transmission line pulse measurement
and failure analyses have shown that the proposed body current
0 ]. X/ P" F  f1 einjection technique can significantly improve the ESD robustness
of HV nLDMOS.
9 N8 F, X. L& o, v
/ X/ {; V; `0 H/ e5 IIndex Terms—Bipolar-CMOS-DMOS (BCD) process, body
. W4 q9 s2 A# W) O8 b0 {current injection, electrostatic discharge (ESD), lateral double-diffused
9 n$ T% H) y3 ^0 i; V7 rmetal–oxide–semiconductor (LDMOS).

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