Time | Speech/
! N# a: a5 p6 P. K- ~% CPlatform | Topic | Speaker |
09:00~09:30 | Registration |
09:30~09:40 | Opening | Welcome Remark | Veronica Watson,/ h) h; v3 s7 o ]$ _2 D
AP President of Cadence Design System
5 D- N" W) t' P3 E2 [" }Willis Chang,
! X6 h5 s, E- v9 I$ {% x% {Country Manager of Cadence Taiwan
4 C, B; v3 W# D8 q" o5 @9 g |
09:40~10:10 | Keynote | EDA 360: The Way Forward for Electronic Design | Charlie Huang,
$ X8 A4 e2 X. |Senior Vice President and
+ E8 @1 B7 z0 F) JChief Strategy Officer |
10:10~10:40 | 4 q- i6 D' u, B6 c/ ]8 P3 x
Keynote | Cadence open integration platform with integration-optimized IP | Brian Gardner, 6 k P* v& Q; L/ w4 p" Z
Group Marketing Director, New Business, Cadence |
10:40~11:00 | Break (Proceed to Breakout Rooms) |
Custom Design
8 z4 v; @) ~* M& Z' p$ f(Meeting room A&B, 13F) |
11:00~11:50 | CD01 | TSMC AMS Reference Flow | M. J. Huang, 4 P0 v# G" W% M
TSMC |
11:50~13:30 | Lunch |
13:30~14:20 | CD02 | Virtuoso IC Design Platform 6.1.4 - Analog Design Exploration and Optimization | Alex Wang |
14:20~15:10 | CD03 | Virtuoso What's New 6.1.4 - Virtuoso Advancing the Art of Custom Design | Kevin Tsai |
15:10~15:40 | Break |
15:40~16:30 | CD04 | Advanced 32/28nm Node Challenges & Solutions - Enabling Fastest Time-to-Volume | Eason Lin |
Functional and System Verification 3 H$ G3 X$ a6 ~- D
(Ballroom C, 10F) |
11:00~11:50 | FV01 | Predictable System Realization | Michael McNamara |
11:50~13:30 | Lunch |
13:30~14:20 | FV02 |
, S! Z* k3 n9 N; w% uCadence TLM Design & Verification with C-to-Silicon Compiler | Mark Warren |
14:20~15:10 | FV03 | Cadence TLM to GDSII flow | Rich Owen |
15:10~15:40 | Break |
15:40~16:30 | FV04 | Cadence TLM Verification | Cadence Expert |
Digital Implementation
0 G& \* ? [5 T& m- |' F9 |* P(Ballroom A, 10F) |
11:00~11:50 | DI01 | Digital Implementation Update at TSMC Reference Flow 11 | Cadence Expert |
11:50~13:30 | Lunch |
13:30~14:20 | DI02 | DoT/MSoT for Mixed Signal Demo | Mladen Nizic |
14:20~15:10 | DI03 | EDI System Roadmap: Encounter Digital Implementation System - Enabling "More than Moore" | Wei Lii Tan |
15:10~15:40 | Break |
15:40~16:30 | DI04 | EDI System 9.1 Update | Cadence Expert |
Logic Design / E; q8 V1 V0 m8 b" c
(Ballroom B, 10F) |
11:00~11:50 | LD01 | Cadence Logic Design Product Roadmap | Yoon Kim |
11:50~13:30 | Lunch |
13:30~14:20 | LD02 | Phyical Predictability in RTL Compiler Synthesis | Mark Ou |
14:20~15:10 | LD03 | Conformal ECO Designer | B. C. Shih |
15:10~15:40 | Break |
15:40~16:30 | LD04 | Can your spreadsheet do this ---- Innovative applications of pre-RTL chip planning | Anis Uzzaman |
System and IC Packaging % P4 U6 S. w. h- U' N4 s& g' [3 Z
(Meeting room C, 13F) |
11:00~11:50 | SPB01 | SiP and 3DIC/TSV Design in TSMC Reference Flow 11.0 |
1 h9 b d( S9 y5 u: W7 }3 P( NMike Peng, ' P6 y" I3 N% b
TSMC |
11:50~13:30 | Lunch |
13:30~14:20 | SPB02 | What's New Update for 16.3 Allegro Package Design and SI Simulation? | Joseph Kao Z6 P3 k' `4 c# Z; g2 b! [
Thunder Lay |
14:20~15:10 | SPB03 | Distributed Co-design for IC-Package-Board | Thunder Lay |
15:10~15:40 | Break |
15:40~16:30 | SPB04 | Design issues from IC to package: Managing Package Outsourcing Engineering | Kevin Liu |
16:30~16:45 | Lucky Draw(Ballroom A, 10F) |
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