your input command mode rage is 0 to Vdd - (Vsg1+Vdsat5); l2 i! a+ a$ ^1 X$ K% K
output command mode range is Vdsat7 to VDD-Vdsat6 - U! x* \. @! Z4 Y1 l" }& V 6 H# Q$ q1 q3 d% n0 Wif this opamp is connected as unit gain buffer, ( k. V7 g6 D2 h w5 o! C; m; _1 [then the input & output command mode rage will be the same as vdsat7 to Vdd - (Vsg1+Vdsat5) - W' ]8 F+ F# D- Q6 Y( |8 }& ]* a5 P0 M& Z* V
don't trust simulation too much ! 5 ^0 k" i4 ~: v3 x: v+ HIf you really want to design a real world opamp.
謝謝chungming大的回應7 c1 {8 l2 P G2 _
可以請問一下，考慮上述in/out common mode的情況下+ p ]2 I( c6 m/ u9 g6 u
接成UGB為何在模擬上仍可從foll ...5 Q8 R T$ Q2 g3 W4 }' _& a
Bookert0921 發表於 2010-5-28 10:44 AM
[複製鏈接]
IP卡
狗仔卡
發表於 2010-5-27 23:50:01
顯身卡