關於時序約束

cosmosd

各位，在綜合或者後端，輸入的input delay,output delay都是針對輸入輸出管腳，那麼對於模組或者系統內的中間信號呢？工具是自己根據庫工藝參數進行優化？那麼內部的優化有沒有裕量啊？由於工藝的偏差，又怎麼保證內部信號的時序對呢？

yytseng

跑 STA (static timing analysis) tool

2 Y& ?3 }4 z% U/ c( `4 v& X; Oex. synopsys primetime,  or cadence timing system

lee100

STA only cover synchronous design. Designer has pay attention for asynchronous design make sure clock frequency and waveform same as function mode and all flops must constraint by its clock.