由於之前都用CIC的虛擬製程.這是第一次用真的製程所以我完全沒有頭緒.請各位前輩幫幫忙.謝謝 4 P' [0 A& H# K+ V我LAY完一個子電路後跑DRC.但它出現以下幾個錯誤...(幾乎都是同一類錯誤.超多) $ z" w3 a$ Z+ W/ ^1. DOD.R.1 {@ DOD is a must. DOD CAD layer must be different from OD's. a' y' \, x0 [1 K2 h( v
CHIP_CHAMFERED NOT INTERACT DOD } , y! n5 W) t7 N A1 ]6 o# K2. CSR.R.1.NWi {@ NWi is not allowed inside the empty area of chip corner. [8 T5 Y7 I+ Q0 x! N7 @
EMPTY_AREA AND NWi } $ r& o; Z' |7 `. I3. DUTM.R.1 {@ DUTM is must. The DUTM CAD layer must be different from the the UTM CAD 9 V$ h3 v( ^7 U/ R! l
layer. + y' `) r" n6 u: `* D/ v3 P/ E9 ^; t CHIP_CHAMFERED NOT INTERACT DUUTM }8 x5 h7 {% b5 D& u% L* Y" ~2 X