library compiler建DFF cell的疑問

霜淇淋

各位好，小弟打算跑HSPICE改變一下cell library的資料
但有部分還是不太理解，以下是D-Flip Flop(DFF)接腳D及CLK部分
1 D" M( W5 j$ A
: _8 s5 R; K9 i, [
: G# o+ [/ H2 G8 \( ~  pin(D) {
! \4 {% W7 @9 d2 {( r1 q0 ]    nextstate_type : data;
# W6 I; i( O) }' I/ m8 I9 N    direction : input ;
    capacitance : 0.001165;
" a0 e* Q0 q- Q# l/ R! K) H    internal_power() {
      when : "!CK";
      power(POWER_7x1) {
7 h, w2 _% c& }- H        index_1("0.009652,0.016106,0.025992,0.046675,0.088958,0.216628,0.447814");
        values("0.003651,0.003635,0.003626,0.003611,0.003614,0.003725,0.004117");
      }
& ^2 X: [8 {) F    }

values值是指不同的D端電容(index_1)在CLK=0時的POWER值嗎?
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; Q7 L* h& W% T* \( q  B    internal_power() {
      when : "CK";
      power(POWER_7x1) {
8 k* o  g, x3 A2 L        index_1("0.009645,0.016106,0.025991,0.046674,0.088957,0.216628,0.447814");
        values("0.000127,0.000122,0.000120,0.000119,0.000117,0.000116,0.000114");
" Z8 x/ X, D% d7 L      }
    }
    timing() {
      related_pin : "CK";
      sdf_edges   : both_edges;
      timing_type : setup_rising;
0 V, C  f; p5 Y' P' {$ H      rise_constraint(CONST_3x3) {
        index_1("0.006000,0.217000,0.434000");
        index_2("0.006000,0.108000,0.217000");
9 G* y7 q  x/ e1 X        values("0.029659,0.026470,0.036963",\
" J. {2 ~) K& M; Y* n               "0.032032,0.023912,0.031939",\
               "0.004917,0.000010,0.004825");
      }
/ c, e& A9 j# {! M! z
# I/ P7 f- s0 A( o" ^0 evalues是指DATA輸入transition time(index_1)跟CLK輸入transition time(index_2)不同時所得到的setup timing嗎?
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      fall_constraint(CONST_3x3) {
        index_1("0.006000,0.217000,0.434000");
* o1 [& C& i8 p        index_2("0.006000,0.108000,0.217000");
        values("0.074043,0.058526,0.059156",\
/ x1 z( s2 Z- x1 T5 c7 Z               "0.152860,0.139810,0.137970",\
               "0.231770,0.216260,0.216890");
3 z5 y8 O2 T2 R5 i; ^5 ~. w8 ?2 G      }
    }

yytseng

internal_power() {
      power(POWER_7x1) {
        index_1("0.009651,0.016105,0.025992,0.046675,0.088957,0.216628,0.447814");
4 I& N' I; a3 D, U' O- B$ i9 l        values("0.004066,0.004029,0.004007,0.004000,0.004050,0.004346,0.005062");
( o# f' ^1 p7 r( S- W6 t& u8 Jvalues值是指不同的CLK端電容(index_1)在CLK=0時的POWER值嗎?
5 J9 I! k! B1 t1 q===> Wrong !
( }/ x, W3 _# G5 X===> they mean while different input slew (transition) of CK, results different internal power
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1 i( n1 v( O7 P: t1 K" vmin_pulse_width_high : 0.061268;
; s# d, E# }2 |; J2 |" |2 ?: hmin_pulse_width_low  : 0.125320;
: p8 M$ p9 T! z( e" X# X& RCLK Hi/Low的長度?
7 B; K4 {; d; b====> No, these mean minimum possible of clock waveform to prevent functional fail, for high (1) and low (0)
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      index_1("0.009652,0.016106,0.025992,0.046675,0.088958,0.216628,0.447814");
* ?9 W4 S) T7 D0 a- K        values("0.003651,0.003635,0.003626,0.003611,0.003614,0.003725,0.004117");
      }
    }

8 c2 _, r$ d' ~  t" _2 qvalues值是指不同的D端電容(index_1)在CLK=0時的POWER值嗎?
==> No, index1 is often input transition. here represents input slew of D pin
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6 b  U5 q# _0 c" o  D) ~- c        index_1("0.006000,0.217000,0.434000");
        index_2("0.006000,0.108000,0.217000");
        values("0.029659,0.026470,0.036963",\
: {8 x7 b& r( {7 c               "0.032032,0.023912,0.031939",\
/ e) h& x5 p) ^  z               "0.004917,0.000010,0.004825");
      }
3 s3 @* O  U, [  I
2 V0 ~/ F$ ^1 a4 F- }0 _; K5 Ovalues是指DATA輸入transition time(index_1)跟CLK輸入transition time(index_2)不同時所得到的setup timing嗎?

1 l& N* j. j5 E9 \/ L" P===> yes, but you have to refer index_2 definition in the front of liberty file to make sure.

霜淇淋

timing() {
. v' `4 ^  M; h) E; S, q+ C      related_pin : "CK";
      sdf_edges   : both_edges;
      timing_type : hold_rising;
      rise_constraint(CONST_3x3) {
  g+ \$ B+ Q/ Y6 ^  R+ x- g. j        index_1("0.006000,0.217000,0.434000");
( a' f% r# }) e0 B! h0 T        index_2("0.006000,0.108000,0.217000");
6 f; [1 x: x. o: y        values("-0.005932,-0.005209,-0.015703",\
; V! N  J- W3 Z1 f+ g% K( v4 q, }               "0.013887,0.014610,0.004117",\
- W8 ?7 ?7 G8 A7 ?               "0.060728,0.056519,0.043560");
8 I" M8 G, n" K& N) u: d( Y      }
: D/ A" B  O( S0 E0 @' A      fall_constraint(CONST_3x3) {
        index_1("0.006000,0.217000,0.434000");
        index_2("0.006000,0.108000,0.217000");
/ W9 G9 U" E) B8 U) `: W5 ~( P        values("-0.018261,-0.002744,-0.005839",\
               "-0.028829,-0.021521,-0.028745",\
5 e, k% n. _# I  f2 |               "-0.004426,0.053203,-0.004342");
      }
' l* V% B" P( ~/ j0 d* u  z    }
3 x$ G) `7 `1 F  f' N, |  }
6 R! H, ^, a* [# b4 e  pin(CK) {
    direction : input ;
    capacitance : 0.001915;
    max_transition : 0.217000;
. H! o- L) v0 [& a$ o4 V# _    clock : true;
- K9 S* r3 L. k    internal_power() {
      power(POWER_7x1) {
        index_1("0.009651,0.016105,0.025992,0.046675,0.088957,0.216628,0.447814");
' s" z# @0 A# B9 p3 u& b        values("0.004066,0.004029,0.004007,0.004000,0.004050,0.004346,0.005062");
      }
0 C( ]- J% W* \; A, l; i/ K  @    }

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4 A: Y4 W5 Q& dvalues值是指不同的CLK端電容(index_1)在CLK=0時的POWER值嗎?

8 @/ `* h" s3 d8 N! X    min_pulse_width_high : 0.061268;
    min_pulse_width_low  : 0.125320;
9 W1 V8 V; J& J% q( ?  p5 @9 [" J( q) D
CLK Hi/Low的長度?
  }
}
* n' S' ~0 t  p; }

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有觀念誤解的話希望幫忙修正..謝謝

. o2 H$ m# m1 z( I' P* m[ 本帖最後由 霜淇淋 於 2009-9-17 02:03 AM 編輯 ]