|
In order to save test device, usually will do Power to Ground then IO to Power/Ground and the last is Io to IO. ) \5 f ?6 o# I, g. D, o
2 P- N5 `0 {" ]* x% u0 j0 o
The reason is:
4 r+ i- P, [1 G, Q1 M8 y I) i+ h) h7 `1. If power to ground can not pass, the rest combination has less chance to pass1 k: j- K$ n% P0 x- p$ R2 d
2. Usually power pin count is less than IO pin count. It is fast to get an idea how the chip's ESD level
' {: A5 Q( M0 P; E3. If failed, it's easy to find the failed ESD zapping combination |
評分
-
查看全部評分
|