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In order to save test device, usually will do Power to Ground then IO to Power/Ground and the last is Io to IO.
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3 i1 T# l# Q8 ]: GThe reason is:
/ {( ?4 H8 q+ ?+ h# f# G1. If power to ground can not pass, the rest combination has less chance to pass
5 L4 n: y6 _5 H/ M6 l5 R1 A) R5 J0 }) S2. Usually power pin count is less than IO pin count. It is fast to get an idea how the chip's ESD level
" q7 p' L- S4 b# R- @$ y3. If failed, it's easy to find the failed ESD zapping combination |
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