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Synopsys R2G flow, ^5 e# V* K* C' G3 h( S
1. rtl simulation by vcs J) N& B2 l% t! X# m7 G
2. synthesis by design compiler ultra with dc/dct mode
8 H* f, E. }; _$ H( K5 }4 ]* ?& _3. dft insertion by dft compiler- G/ x8 t A2 J: H' k/ L7 ?
4. jtag insertion by bsd compiler8 p- z2 ~& \5 i N+ b9 a7 h
5. ICG insertion by power compiler; r% ~. I* t/ ]6 b8 E, E* ?
6. pre/post-layout STA by prime time
! d, h. O, N& D/ @7. pre/post-layout power analysis by prime time px
. _' t$ e& d X( ]8. PnR by IC compiler2 I2 V4 _9 Q, F; a) r
9. post-layout SI analysis by prime time si9 M$ Z' L2 q2 x( ]' @
10. post-layout simulation by vcs |
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發表於 2009-5-19 10:30:14
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