請問由Verilog code到IC layout 需要哪些軟體

leesg

問題, 已完成 Verilog code 設計, 模擬(ModelSim)
1 e& G8 a! M' t% z" i想要用軟體直接 run 到 IC Layout 產生 die photo,
  Z/ L/ Z6 {) h( i* y( x' a- Q7 m要用什麼軟體組合 ? (輸入 verilog code, 自動跑出 IC Layout)
2 {* V5 X, R  N" S1.
design compiler + Astro ?
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2.
/ K! T8 y8 c  @4 \synopsys IC compiler ?
# E* O1 L3 A, l6 u* G0 D8 f0 @
3.
cadnece virtuso ?

lee100

Synopsys R2G flow
1. rtl simulation by vcs
2. synthesis by design compiler ultra with dc/dct mode
7 d+ \) C& J9 `* _8 k( d6 p$ P- U3. dft insertion by dft compiler
0 O7 T8 G5 g! [" l' H4. jtag insertion by bsd compiler
5. ICG insertion by power compiler
6. pre/post-layout STA by prime time
7. pre/post-layout power analysis by prime time px
8. PnR by IC compiler
9. post-layout SI analysis by prime time si
10. post-layout simulation by vcs

putechen

sometimes ,star-RCXT is necessary.just for layout PEX.

yytseng

after above place and route task, you need virtuoso or laker to merge cell layouts and do some editing.
  B9 \+ q/ V$ u% j$ F! B( c5 yclean up LVS/DRC/ERC/ESD violations with calibre or (hercules, assura) tools.

ejean

1. magma is another solution
# }5 U& @' c. B& G) y2. Astro  from synopsys
3. FirstEncounter from Cadence
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. Y7 @4 S7 t, E: @2 e1 WAll with basic DRC and LVS, you have to run Calibre, etc. to finish the final verification.

ilovepachaya

私心推薦APR使用IC Compiler  效果很好