There's a career in Analog/Mixed-Signal? Where's A/MS Talent in Taiwan?

ranica

招聘公司：a fabless IC design company
* B4 D  y4 c) S" E( s, W$ w招聘岗位：Junior/Senior VLSI Designer
" x* a/ K9 ?3 f! z+ V  Q5 K3 q工作地点：Shanghai

岗位描述：
5 J# e8 U# y  K* d- ~Responsibilities: 1. Chip level micro-architecture design for digital TV and Set-Top-Box applications. 2. RTL level design and system simulations. 3. RTL to netlist synthesis, formal verification and timing analysis. 4. JTAG boundary scan and full scan chain implementation as well as ATPG vector generation.
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职位要求：
. E, v2 H# L2 O/ F& _- ^( Q( qRequirements: - BS or MS degree in EE with 3+/5+ year VLSI chip design experiences. - Skills and experiences in DTV SOC design, computer system, 2D/3D graphics, digital audio DSP processor and/or networking chip designs. - Experience in RTL simulation tools, Synopsis logic synthesis tools, Formal verification tools, timing analysis tools, and Design-For-Test schemes. - Knowledge and technical background in one or more of the following areas are necessary: Computer architecture, PCI bus, USB, ATA bus, IR, UART, SmartCard, 1394, Ethernet, DDR, SDR memory systems will be helpful - Good communication skills and self-motivation!

ranica

招聘公司：digital audio chip maker
招聘岗位：模拟IC设计工程师
工作地点：Shanghai
* @# E( r6 r: `" X
岗位描述：
岗位描述： 1. 设计模拟电路或混合信号IC。 2. 使用CADENCE或MENTOR GRAPHICS设计工具进行模拟电路设计，仿真。 3. 设计版图布局，并协助版图工程师进行版图设计，确保版图达到电路设计的要求。 4. 计划实验室评估计划，并使用实验室测试设备对工程样片进行测试评估。 5. 撰写设计，测试报告,协助测试工程师进行中测和成测规范的定义和程序开发，验证。
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! M) H& ~4 {! [" v职位要求：
& E/ B/ }! n9 @职位要求： 1. 具备扎实的电子电路和晶体管的理论基础，掌握IC设计流程、方法及工具，熟悉集成电路制造过程和工艺。 2. 熟练应用Cadence设计软件进行IC设计。 3. 熟悉模拟电路的原理，设计技巧及关健参数，如参考电压源，振荡器，放大器，比较器等。 4. 具有良好的学习，分析和创新能力，良好理论与实际结合的能力，在电子电路方面有良好的悟性。 5. 具有模拟或混合信号IC成功量产经验 、硕士研究生或以上学历。

ranica

招聘公司：A communications chip company
2 v8 }4 x! b9 d招聘岗位：内部审计
工作地点：Shanghai

" A# e/ s0 Q: F+ o: B- B岗位描述：
8 B& k! [" e1 B. d! b0 h- O工作目的和性质：在审计监察部经理的领导下，开展与内控管理相关的组织、协调的相关工作，负责组织对下属分、子公司的审计监查组织工作。 主要职责： 1. 对内部控制及风险管理的有效性进行评审，推动建立、健全内部控制系统。 2. 制定公司内部审计制度，负责审计项目的调查，拟订具体审计方案，出具审计计划与审计通知； 3. 编制审计工作底稿，并收集、整理和归档各种审计资料； 4. 对被审计单位财务收支及其他业务活动的真实性、合法性、合理性、效益情况进行独立的经济检查和监督； 5. 实施审计调查，控制、考核、纠正被审计单位偏离公司整体经营目标的行为； 6. 编制审计报告并就审计结果对财务及经营管理提供有效、可行的建议； 7. 开展内控审计，对公司内部控制制度的建立与执行情况进行审计； 8. 参与经营管理方面的内部控制程序和制度的制订； 9. 综合管理部/审计监察部经理安排的其他工作。
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' Z! c* W* K& f7 j9 M职位要求：
任职要求： 1. 学历要求：全日制大学财务、审计类专业本科以上学历，持有CIA资质者优先考虑。 2. 工作年限：8年以上企业内部审计监察工作经验 3. 其他要求： a) 坚持原则，廉洁奉公，忠于职守； b) 有较强敏锐的洞察力、逻辑分析能力以及较强的持续学习能力，富有创新意识； c) 熟悉财会、税收等相关经济法律法规，熟悉企业内部控制与经营管理；熟悉内部审计的规范、程序，了解企业风险管理与控制； d) 优秀的文字表达能力； e) 熟悉应用各类办公软件； f) 良好的沟通与团队协作能力，良好的亲和力和应变力； g) 具有较强的自我学习能力和独立开展工作能力； h) 积极主动，能在压力下工作。

globe0968

聘公司：one famous IC company
招聘岗位：Sr. Design Engineer
工作地点：Shanghai
7 J% O: N: l$ F' }
岗位描述：
-Work with analog power IC design team for new product development; -Work closely with layout designer for layout implementation -Verification of performance requirements using appropriate simulation and verification tools. -Support test & product team with chip debugging, failure analysis, characterizations and product release efforts;
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# o% G  {+ p: o8 L% S' @职位要求：
-Master degree or above in EE or related field; -3+ years of working experience on analog power IC design area; -Familiar with details of product development: design method, design process, CAD tool, design for test, physical design, system applicant -Strong experience in power analog blocks design, including LDO, DCDC Converters, Battery Charger, WLED Driver, Power Path, Charge Pump, etc. Especially on switch mode converter designs. -Familiar with CAD tools, such as schematic capture, SPICE simulator (or equivalent transistor level circuit simulator), Virtuoso; -Understanding of BiCMOS process technologies and device physics -Excellent understanding of written English and good spoken English -Good communication skills and cooperative spirits. -Outstanding ability of self-management and attain goal under pressure.

tk02561

招聘公司：A famous IC company
招聘岗位：Senior / Design Engineer ( Memory)
0 L. @; r* ]7 z# v# L工作地点：Shanghai

3 _6 j; ^+ f3 }8 @岗位描述：
-Responsible for analog and logic block design in the memory products. -Responsible for the developments of non-volatile memory products and flash macros.

职位要求：
9 ~' t6 u" X) E5 S- u. kKey Competency Requirements: -Technical knowledge in IC design methodology. -Knowledge of non-volatile memory, analog design, noise analysis, low power/leakage, high-speed memory design a definite advantage. -Tools used may include HSPICE/HSIM, Cadence Design Entry, IC layout tools, or other equivalent tools. Education and Experience Required: -Education Required: MS. EE or Ph.D. EE required; -Experience Required: 3+ years memory or analog design experience; -Advantageous with experiences or exposures to the following: as project or team leader, test, package/assembly design and digital/layout design.

ranica

职位描述
' Y3 k7 _8 Z* R1. Application engineer on high power semiconductor devices (e.g. IGBT modules & discretes) for industrial & consumer applications.
( v5 \! b6 H. U$ C4 ?/ r8 k. s2. Technical support on power semiconductor product promotion, application & training for regional customers and distributors.
0 q. U% j1 u( V7 ^" I& }- U 3. Co-work with marketing & sales colleagues on project understanding & tracking.
4. Domestic & occasional overseas travel required.
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职位要求
- Good educational background with Master (preferred) or Bachelor’s degree on Electrical/Electronic Engineering (majored in Power Electronics)
- Good professional background with at least 5 years of working experience
- Hardware & PCB design experience on inverters/converter power stage for AC drives, UPS and other power conversion equipment.
% j9 V, B; T: {* }7 f9 Q8 E - Familiar with PCB CAD software tools (e.g. PROTEL, OrCAD, EAGLE) and skilled in making schematic diagram and PCB layout
- Knowledge & experience with IGBT switching, gate driving, protection, cooling, power layout and system issue like EMC treatment.
- Knowledge on power electronic circuits and applications like AC drives, UPS, welding, induction heating, wind/solar power generation, etc.
" L+ ~+ H& k1 y9 T- Good language skills in Chinese and fluent in spoken & written English
( v% U* h% x! ^1 k- Strong analytical skills and self-learning/quick learning ability
6 O% K6 g8 T9 @' P% k! `- Good interpersonal skill and good team player
- Highly initiative, self-motivated and result-oriented
1 ~' K$ j. ?5 ~ - Willing to be dedicated in technical job and taking it as long-term career

ranica

客户 A famous IC company
; @1 `. V! O- D2 k" N# m地点 Shanghai

职位描述
- B) d* X  b3 J6 F' R1. Quality interface between XX and wafer foundry & EPI vendor.
  |* p! e$ t; p 2. Coordinate monthly business review meeting and hold regular quality review meeting with wafer foundry.
  ^7 ]4 l% Z5 m9 ]( ] 3. Work with engineering groups and wafer foundry to solve wafer quality issue.
4. Dispose wafer related nonconforming material.
# ^# b1 {9 U4 S# f 5. Handle failure analysis for quality issues with foundry and handle wafer RMA.
6. Establish and maintain quality metrics to evaluate foundry quality performance.
7. Review foundry 8D/CAR and verify corrective action implementation and effectiveness.
8. Lead wafer foundry audit.
0 o3 w* Q- {& A0 `8 g6 \# | 9. Work with internal integration team to manage foundry change control and follow up XX ECN implementation.

ranica

职位要求
Items Necessary Qualification Expectation Qualification
Education Bachelor degree or above in  engineering.
Experience
9 v1 X' l; Y* s4 t4 V# c8 V Min 3 years experience in wafer fab. Fab process or quality engineer  preferred.
Skill
4 Y2 V- ^- E0 }2 {) R Experienced in 8D & problem solving  and SPC
4 \( a* b5 Y5 i) F' g Familiar with Wafer level FA
" J  M5 _3 P4 ]5 |; R: G8 x0 C  v4 z8 A Qualified ISO 9001 or TS 16949 auditor
; F9 r9 d) g- h: B  h Competency
& @  p: N& `; G; L  n* V7 \5 Y Good written and spoken English.
* E* g+ \/ a- I7 {7 F Semiconductor manufacturing  experience
Be able to work and communicate well  with all levels of external manufacturing  suppliers.
8” fab experience preferred
# I! m+ @( X) B7 l% ` Power device (discrete & IC)  experience preferred
Personality
Good Initiative,
. q: o" m& f( r2 x Good executive,
Good teamwork.
5 }4 S1 E; E1 _. b Activity scope
7 Z, ]& Q, Z% n Environment
Location(work place): Shanghai
Work time( part time/full time): Full Time

ranica

招聘公司：a top 15 semiconductor company
( _1 s8 ]: e6 a招聘岗位：PLC AE
工作地点：Shanghai
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4 T: l+ V2 k/ Q2 J岗位描述：
1 N: T6 M) P/ p5 w8 n: `. ^# w  Do Conduct field trials (Coordinate Installation, Debug installs, monitoring of systems performance, analysis of results) o Guide development team in various customers focused areas – Available SWR/HWR tools, product features, ease of use o Technical Support customers with design in of OFDM PLC ICs, Production ramp up of modules, system integration of XX’s PLC solution into other equipment o Writing of Technical Documentation and customer/partner trainings o Initial design/localization of PCB modules

职位要求：
- Be self-motivated with a strong desire to learn new things and work in a developing technology area. - Able to communicate effectively in English - Good communication skill and team work ability - Have excellent troubleshooting skills including hands-on experience conducting experiments with lab equipment. - 5+ experience and good understanding on developing Hardware and Firmware for embedded system solutions (in C) - A bachelor's degree in Electrical Engineering (BSEE) or equivalent. - Experience designing mixed signal circuits for OFDM PLC communication systems and protocols is a plus - Be able to travel often in China

ranica

招聘公司：A famous IC company
; Z  A8 t0 W8 C2 F' v+ i招聘岗位：Regional FAE Director
$ \1 @* P5 Y) M! O4 Y; V3 b' U工作地点：Shanghai
7 m3 c- ~8 i6 n8 p7 `& D
# }# G/ _' `1 c; s4 n) C+ A岗位描述：
1 ]  H& s: {, o0 Q2 i/ J- ~· Manage field application engineering team and global power resource center (GPRC) in China. · Develop technical support team both in technology capability and skills to support business. · Lead technical support team to provide best technical support to key customers, to increase xx penetration in China. · Coordinate communication between sales, product line department, marketing and technical support, to develop and execute China strategy. · Coordinate communication between technical support team, marketing and product line department in new products and new solution development. · Identify technical trends as well as current and future customer system requirements · Coach technical support team to maintain moral and passion and team’s stability.
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职位要求：
# T: ^+ Y: c; D- {- \6 E& v· 10+ years experience in technical support or R&D. Experience and knowledge in power supply is a must. · At least 5 years experience in leading technical support team across region. · Good communication in diversified team members, be confident to gain others’ respect and trust. · Strategic thinking, good in business sense, be able to develop technical strategy. · Good in motivating team members to achieve goals, especially under pressure.

ranica

招聘公司：A famous IC company
招聘岗位：资深模拟设计工程师
工作地点：上海，成都，南通
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岗位描述：
1. 电源产品（只要是DCDC以及PMU产品的设计，特别是大电流DCDC产品的设计）。 2. 与销售和FAE人员一起制定产品的指标。 3. 与Foundry一起沟通选择最佳工艺 4. 指导版图工程师的布图 5. 与实验室测试工程师（AE）和量产（ATE）工程师一起制定测试方案。
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职位要求：
3 L* {( ?$ x; Y5 P3 m1 ~6 j1. 本科毕业，硕士和博士毕业优先考虑 2. 5-8年以上电源管理产品的独立的设计经验，具有PMU产品的设计经验优先考虑 3. 熟悉低压CMOS，BiCMOS，以及高压LDMOS等器件的物理结构和工艺制程 4. 熟练使用英文与其他国家和区域的帝奥团队沟通。

ranica

招聘公司：A famous European IC company
( ~' P5 T4 \# i, r: i/ ]招聘岗位：Sr. IC design engineer
4 f3 P$ ?* j3 D7 o6 i& _. _工作地点：Shanghai

+ G& [1 L/ ~) z2 s3 p岗位描述：
/ {2 c0 h! c# o+ `3 ]3 c' [# |Roles and Responsibilities - feasibility studies of circuits and systems (incl. HW design) - support product proposal and definition - analog IP and subsystem design and verification - top-/systemlevel verification - IC evaluation/debugging - test proposal and support transfer to production - plan and track project activities - coach junior engineers and interns
* m$ c7 e# X0 {( c% G6 B8 n
职位要求：
2 K4 f8 }6 }/ h/ Y" ^! XQualification Requirement (e.g. Education, Working Experience, Knowledge, Skills, Language, Competence, etc) - master degree in microelectronic circuits or systems - > 5ys experience in Smart Power Design - good understanding of ASIC analog and mixed signal flow (Cadence based) incl. toplevel integration/verification - strong background in smart power s/c technologies - experience in DC/DC converter and DC motor driver/control design - hands-on experience in silicon evaluation and debugging - very good communication skills, team work and high degree of flexibility - foreign languages: English, German (not a must)

ranica

聘公司：A famous IC company
" {7 F  ^% v" ?. \招聘岗位：Sr. WLCSP development engineer
工作地点：Shanghai
- k( r. A8 C4 T; s
岗位描述：
: T/ O; p! \6 W) Z1) Act as WLCSP RD project leader for all the WLCSP related activities. 2) Integrated with Process / Product Engineering, Production, QRA, Final Test and Maintenance teams in the WLCSP assembly problem solving. 3) Developed new WLCSP packages from feasibility, design, process development, qualification to mass production. 4) Design the new WLCSP package for new application or performance improvement. 5) Improve the WLCSP assembly processes for cost effectiveness
. O" N$ @  b; c4 [) R: _
职位要求：
(1) Bachelor, Master degree or PH.D. in Mechanical/ EE/ Automation/ Material Science, etc; (2) 10+Yr working experience of semiconductor WLCSP design/development or package R&D related field; (3) Experience with WLCSP NPI project as plus; (4) Good knowledge on mechanical design/simulation(Ansys or other software), material analysis, package assembly process, package qualification method, project management; (5) Ability to achieve results in a fast moving, dynamic environment. (6) Good team work, willing to learn, and logical thinking; (7) Good English communication (written and verbal) and interpersonal skills.

ranica

Senior Design Manager
- P; p  W' E( F" g  S/ d7 r) P2 w# h客户 A famous IC company
地点 Shanghai
) ^# G( L8 _) H" I% a9 ~
职位描述
Duties
Analog IC circuit design, simulation and verification
Design analog products and blocks such as high current, high voltage DC-DC etc.
: N. x3 W; }/ k" _# {Design of the switching power IC, Charger, Load switch etc.
Evaluation, simulation and analysis of power architectures and circuit topologies
2 ?$ F1 c& ?1 GMixed-signal circuit design, verification
IC layout including floor planning, DRC, LVS, and LPE
, M8 p; d  D4 }( u& KWork with application and testing engineers to define optimal characterization and testing solution
: J* N* g5 x# @* T, |Work with product definers and product engineers in full product development flow
Work with product line to coordinate/lead projects, accurately scopes out length and difficulty of tasks and projects. Establishing clear directions and set stretching objectives
: n% x* J& b1 |4 QBuilding and creates strong morale and spirit in his/her team.

ranica

职位要求
Requirements
Minimum 10 years direct DC-DC IC design experience, with MSEE or above degree
# C- i/ h1 z7 k, K/ pAt least 5 years leadership experience in leading a mid-sized team
% o& p" P. D, U) d# eStrong knowledge in analog CMOS and Bipolar IC design
Working direct experience with switching power supplies, DC-DC converters, Battery charger, and their various topologies
& T+ W8 s3 |$ ?- XTheoretical understanding of the power electronics, switching power supply topologies
* X7 w. I# e. D, y5 F3 \6 K0 mPrior experience with power management related IC design a strong plus
Knowledge in analog IC layout
8 A% Y2 p5 y3 ?Matlab/Simulink/VerilogA or other behavioral simulation expertise a plus
Result driven and can effectively dealing with ambiguity
, i: T' a5 q3 m# xExcellent written/oral communication and presentation skills.
Understanding others, picks up the sense of the group in terms of positions, intentions, and needs, what they value and how to motivate the group.

ranica

Senior Design Manager
公      司：NO.163-A famous IC company
  Y2 C! x& S  y6 {5 J3 x, ]工作地点：上海
7 H* ~- C4 y) |' W! H
7 F  A2 R# ~) O$ K/ o% QDuties
Analog IC circuit design, simulation and verification
Design analog products and blocks such as high current, high voltage DC-DC etc.
$ ?; h& B' z8 Z2 M: tDesign of the switching power IC, Charger, Load switch etc.
Evaluation, simulation and analysis of power architectures and circuit topologies
Mixed-signal circuit design, verification
IC layout including floor planning, DRC, LVS, and LPE
Work with application and testing engineers to define optimal characterization and testing solution
7 U' `3 ]% [( p9 [Work with product definers and product engineers in full product development flow
Work with product line to coordinate/lead projects, accurately scopes out length and difficulty of tasks and projects. Establishing clear directions and set stretching objectives
) `! ]8 C9 B8 J& O& |) N0 bBuilding and creates strong morale and spirit in his/her team.

ranica

Requirements
1 b  L; Q2 ?# n8 |# J# yMinimum 10 years direct DC-DC IC design experience, with MSEE or above degree
At least 5 years leadership experience in leading a mid-sized team
/ x8 D# V- P3 M- e$ T( W9 pStrong knowledge in analog CMOS and Bipolar IC design
Working direct experience with switching power supplies, DC-DC converters, Battery charger, and their various topologies
Theoretical understanding of the power electronics, switching power supply topologies
& g8 I: s( l# Q, f$ f6 j0 RPrior experience with power management related IC design a strong plus
Knowledge in analog IC layout
" w$ L- a5 J& m+ UMatlab/Simulink/VerilogA or other behavioral simulation expertise a plus
Result driven and can effectively dealing with ambiguity
Excellent written/oral communication and presentation skills.
Understanding others, picks up the sense of the group in terms of positions, intentions, and needs, what they value and how to motivate the group.

ranica

国网资深方案工程师（软件）

公      司：NO.116-A famous IC company
工作地点：上海

工作内容：
1、负责xx电能芯片的整体方案设计。

( [, x) ?6 ^  m* }( A岗位要求：
1，   本科及以上电子或自动化相关专业；
/ Z+ J0 b) T& s, s4 E; }' H, v4 ]2，   有3~5年以上国家电网电表软件研发经验；
3，   做过完整国网单相方案，且实现量产；
4，   深入理解国网单相电能表的各项标准，645通讯协议；
7 @( v1 |, s4 b8 l" t5 j5 Q5，   深入了解单相国网软件架构、软件测试流程、及送检流程；
6，   对国网单相表的硬件有一定了解；
7，   有良好的沟通和协调能力，善于团队合作。

ranica

Senior Physical Design Engineer
7 o5 Q, q% \) ~1 t公      司：A famous IC company
( J( t4 [+ U- `工作地点：南京
8 ]7 {9 W4 L, D8 Z8 O  x$ [$ d; \
4 K) C! K. M0 o  I  q7 j$ oKey Responsibilities  
Depending on experience, key responsibilities will involve some of the following:  
IC implementation from netlist to gdsii, with synthesis, floorplanning, place and route, timing closure, and physical verification.
4 p/ m/ }9 n9 a2 s& xAs a key member of physical design team, your will work on one of most advanced and the most complex chip designed.
Leading a team of physical design engineers and resolving the technical related issues.  
; w' v( t4 t, d5 `- q2 HCrosstalk analysis, power analysis, and static timing analysis.  
! w9 q( T! ?9 CWrite scripts in Tcl to improve productivity.  

Experience: 5+ years in physical implementation engineering  
  Q9 J5 R* o4 O0 P) e8 Q; h  
Essential skills  
) \2 V# N" X+ ~3 AMS in EE required.&#8226roven track records of working independently on place-and-route project running and DRC/LVS/ERC/Antenna debugging skills  
Experience with Magma or Synopsys place-and-route tool set and physical design project implementation.  
Good programming skill. Capable of writing Tcl or Perl.  
Familiar with synthesis, static timing analysis.  
Self-motivated team worker, good verbal and written communication skills in English.  
. W5 o) J6 o1 ^, dTechnical and team leadership proffered. Previous management experience highly desired.  
/ X( s. [7 ^. l" T" R9 J7 h0 b+ ~Experience with synthesis, DFT, and verification is preferred.

ranica

Senior NPI Engineer (SSD Product)

公      司：A famous flash memory company
工作地点：上海
% ^) v. h0 H9 |- F6 \
( j8 K& V, x9 s$ e4 J- yResponsibilities:   
Work with the global engineering teams and subcontractor engineering team to define performance matrix for *** SSD project and program in Shanghai  
+ V) q8 a. Z$ R. n: ?5 B Develop and implement NPI holistic strategy and process for a scalable new product development and implementation process for SSD program  
7 p% D* L" B" L! ~1 v Manage new product capacity planning and scheduling (with IE/ MFG team). Ensure product ramp-up and on-time delivery.   
Develop and implement product end of life processes.   
' E. j' v5 h  W; J7 I" o. p' P( M Work with R&D, MFG, Engineering team to develop and standardize process for new SSD product
7 x$ w" L8 [0 Y' S
Requirements:   
$ O" C: o8 v# p8 h: x, P BS or MS Degree or above in Engineering or technical discipline   
More than 5 years solid experience on new project management of storage /consuming electronics products.  
Excellent English verbal and written communication skills, native English speaker preferred.   
Must have good interpersonal, strong ability to work in a team environment.   
Worked in International environment and can coordinate within different groups (cross functional team)   
( M% h6 b" C! j8 u1 F& { Self-driven