FPGA verification Engineer most difficult job functions?

ranica

Staff Verification Engineer

6 g$ h) K5 B* I3 j4 g7 W公      司：one famous IC company
& o% L% H5 g" d# b工作地点：上海
; [# l" I, R# e8 J; L6 J
Qualifications
4 X' B+ Q; W( h- NMS in EE/CS/ME.  
Minimum of five  years experience.
% T( g) E9 V8 X% \Additional qualifications include: Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills.
Candidate should be familiar with as System Verilog, VMM/OVM/UVM verification methdology.
Candidate should be familiar with industry standard ASIC design and verification tools and flow.
Good knowledge ddr protocol and computer system achitecture would be an added advantage.
Good knowledge of Perl and shell programming would be an added advantage.  
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3 U! T- Q( A2 v0 ~# BResponsibilities:
4 x: M: a6 v! I9 k! H2 s0 t) S-Understanding the expected functionality of designs.
" S8 W; q8 v# O/ I; S2 x-Developing testing and regression plans.
-Designing and developing verification environment.
-Running RTL and gate-level simulations/regression.
9 U* L! X1 z2 x-Code/functional coverage development, analysis and closure.

# D7 B1 Y$ Z% ?" V4 a& B, u) v1 B0 {( CRequirements:
Experience & Skill: 5 Years
4 K3 ~) Z: W# `8 l9 L; v-Design verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).
) U5 ]) F4 K3 J. f/ l' p0 {7 |4 S-Knowledge in ASIC/FPGA design process and verification tools.
1 E4 @8 Y: M. z% {+ @-Familiar with design and verification languages (Verilog, System Verilog, SVA etc.).
. p# F% ~: ^; \+ U; d; ]6 ]- Scripting and automation skills (tcl, perl, makefile etc) a plus.
-Familiar with C/C++.
-Knowledge of DDR protocol a plus.
-Independent and self-managing.

ranica

Digital Design Engineer

* M9 n5 s' R6 G1 c  m& \7 c公      司：A famous IC company
工作地点：上海
* |1 O9 @+ U8 W8 }/ O* I! e
Duties
Work with internal and external customers to understand product requirements.
9 E# m1 D! z1 P8 `Create critical silicon technologies to meet the product requirements.
/ R. |3 s; ?$ O( ^8 CWork out critical design flows and methodologies to execute implementation flawlessly.
4 S7 K8 z- Q4 H6 CDesign and deliver final design through multiple stages like specification, micro-architecture, IP  development, RTL coding, verification, logic synthesis, DFT, timing convergence, as well as helping on physical implementation.
Complete full documentation.
Help and mentor junior engineers.
2 b) ~, w1 w; d9 ^
Job Requirements:  
Solid understanding of all SoC chip development stages is required.  
Hands-on Experience with complex SoC design flow is required.  
Hands-on Experience with RTL coding, simulation, verification is required.
Experience with DFT and timing tools is preferred.
% }+ A1 [9 I6 N9 u4 @4 g: E5 NExperience with ARM platform is preferred.
Experience with low power design flow is preferred.
# ?/ w# m% _0 c$ lExperience with system verilog is preferred.
' H/ P7 V6 l% O& r+ b) H* ?Good organization and documentation abilities  
MS in Electrical Engineering and Computer Science with 4 years of experience in SoC design

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