FPGA verification Engineer most difficult job functions?

ranica

Staff Verification Engineer

公      司：one famous IC company
工作地点：上海
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  B6 q3 ^, r( j- e& VQualifications
MS in EE/CS/ME.  
! h9 E" d0 O8 d4 L* D, HMinimum of five  years experience.
3 t6 A2 Q) p* [0 T6 gAdditional qualifications include: Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills.
& ~* L$ V( @6 @/ _$ Y' B2 ZCandidate should be familiar with as System Verilog, VMM/OVM/UVM verification methdology.
Candidate should be familiar with industry standard ASIC design and verification tools and flow.
Good knowledge ddr protocol and computer system achitecture would be an added advantage.
5 m4 Y: _2 f) T6 h6 {3 `" HGood knowledge of Perl and shell programming would be an added advantage.  
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Responsibilities:
-Understanding the expected functionality of designs.
-Developing testing and regression plans.
-Designing and developing verification environment.
-Running RTL and gate-level simulations/regression.
-Code/functional coverage development, analysis and closure.
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; z/ G( }+ ?' O( i) A" ?: W1 VRequirements:
Experience & Skill: 5 Years
-Design verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).
' q5 f) w( B3 v8 m-Knowledge in ASIC/FPGA design process and verification tools.
-Familiar with design and verification languages (Verilog, System Verilog, SVA etc.).
. J# X6 n! g$ B/ F- Scripting and automation skills (tcl, perl, makefile etc) a plus.
% v' c( Y' l* C$ S% H% J6 u-Familiar with C/C++.
-Knowledge of DDR protocol a plus.
. f# `5 _4 f- h-Independent and self-managing.

ranica

Digital Design Engineer
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5 g$ `5 a, j/ e3 c$ Y' `% K2 m公      司：A famous IC company
5 X" E2 n/ e% m2 F工作地点：上海

3 r/ h, Y( f* u1 eDuties
Work with internal and external customers to understand product requirements.
; n( Q5 V& W! p  O* n6 KCreate critical silicon technologies to meet the product requirements.
Work out critical design flows and methodologies to execute implementation flawlessly.
6 A( x  A( _+ |' l* {2 [; uDesign and deliver final design through multiple stages like specification, micro-architecture, IP  development, RTL coding, verification, logic synthesis, DFT, timing convergence, as well as helping on physical implementation.
2 F6 _6 }) w) u3 s( `$ S$ _Complete full documentation.
Help and mentor junior engineers.

: h8 [$ S2 L8 H: K) A2 p- P. tJob Requirements:  
Solid understanding of all SoC chip development stages is required.  
Hands-on Experience with complex SoC design flow is required.  
Hands-on Experience with RTL coding, simulation, verification is required.
Experience with DFT and timing tools is preferred.
Experience with ARM platform is preferred.
Experience with low power design flow is preferred.
Experience with system verilog is preferred.
7 B* p2 h% \# c0 {( b3 N/ pGood organization and documentation abilities  
' F+ ?  R# ^' R& QMS in Electrical Engineering and Computer Science with 4 years of experience in SoC design

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