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//可直接透過synthesis tool用於PLD,FPGA不可 LUT delay則要採其他方式。" c" ~$ W+ o# V: X+ L* s5 v6 x
//所有註解都要保留4 j. h) u/ E6 y& E( X3 ^; M: C! E
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`timescale 1 ns / 1 ns
* y9 {" Q; R. I2 c* g0 f% E2 k0 Lmodule xclk(sclk,ena,set,outp);
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, i0 F9 z l g3 ?2 |- Einput sclk,ena;
. w$ M8 P, \ m4 p6 ]input [1:0]set;3 |1 s1 q8 p; a, N) l
output outp;
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wire outp;0 T7 f, f3 S+ Z* X3 ~* q6 A
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& J) z: |" M G7 d$ w) r2 j' u- ^/**** Node preservation for nodeA **************/
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1 R" X* W |3 B* ]( u" S) ~+ |, O- |//exemplar attribute nodeA_5 preserve_signal true
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//exemplar attribute nodeA_4 opt keep' |/ o, \& m" E7 X
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/**** The following comment form also works ****/
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//exemplar attribute nodeA_3 preserve_signal true
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//exemplar attribute nodeA_3 opt keep3 Z# M" L% ^% {% _
/ I+ N( f' `; `( t; e7 q% `5 ~/**** The following comment form also works ****/
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/ W g) o; N, g D- M& ?8 c( l& q//exemplar attribute nodeA_2 preserve_signal true! r5 _% u4 E0 K: ?
/ P5 r, q: [, k//exemplar attribute nodeA_2 opt keep3 E/ P+ P/ h2 ?% b: L
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/**** The following comment form also works ****/# z; C H' ~0 e
" M0 w' t4 O: w' O7 a* o5 a2 V7 M//exemplar attribute nodeA_1 preserve_signal true
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//exemplar attribute nodeA_1 opt keep
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+ t! ]/ i2 D5 j k. @$ [/ e/**** The following comment form also works ****/
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" q0 v5 s# K0 U% u- O3 z) F5 s+ K/*exemplar attribute nodeA_0 preserve_signal true
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exemplar attribute nodeA_0 opt keep*/
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. p' ]) o$ p( twire nodeA/* synthesis syn_keep=1 opt="keep"*/;
2 l. L3 U; e a" c8 A( Xwire nodeA_0/* synthesis syn_keep=1 opt="keep"*/;
$ ~% _4 l, |/ ~5 G5 B2 `. K( Rwire nodeA_1/* synthesis syn_keep=1 opt="keep"*/;
5 k: s, P3 D, f' v3 @9 t8 P$ O$ I- ~wire nodeA_2/* synthesis syn_keep=1 opt="keep"*/;
5 y8 C) V( I( Y7 \! Swire nodeA_3/* synthesis syn_keep=1 opt="keep"*/;
3 y' }$ s! Y) L# \. mwire nodeA_4/* synthesis syn_keep=1 opt="keep"*/;
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; V' C" \- [7 X/ j2 G3 e, ?: `( gassign#1 nodeA_0 = sclk & ena;. z, ?; q( z, r; D
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assign#1 nodeA_1 = ~ nodeA_0;
+ [2 z3 X' e" Z6 y+ Hassign#1 nodeA_2 = ~ nodeA_1;
+ s' B% V8 G- [$ _; h4 iassign#1 nodeA_3 = ~ nodeA_2;
' d" `1 h- |1 U, y7 zassign#1 nodeA_4 = ~ nodeA_3;
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2 t- K; \+ \, ^; U0 r) Mreg xout;+ O* \ m$ H3 Z! M5 }+ _: v
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always@(nodeA_1,nodeA_2,nodeA_3,nodeA_4,set)
/ R# t# B3 d* H( D5 j$ q casez(set)
: ~) ]; t0 D% G; W& d% i 1: xout =#1 nodeA_2; R# q0 w: R6 J) [0 J
2: xout =#1 nodeA_3;
% a" X o( m. F. D 3: xout =#1 nodeA_4;; D. A& X; o2 g8 o
default: xout =#1 nodeA_1;
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& y7 Q- F! g! l& l6 ~8 j. _assign#1 nodeA = xout;9 v: q( f/ h( ~4 P( n
assign#1 outp = ena ? nodeA^sclk : 1'bz;
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endmodule
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module xclk_tf();+ r0 k0 b5 m% K
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// Inputs
N" o8 F- Z% a- J7 ?. n reg sclk;3 z1 d Q" y/ f# y6 n3 `
reg ena;. R( J" ^( o8 Z; a
reg [1:0] set;
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O, \) U4 p9 m$ c. M6 g" M// Outputs
$ F9 }% l" J# w; Y) p, j wire outp;
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3 y/ L) a, k* ^2 y" y xclk UUT ( M& e6 w# Q% q
.sclk(sclk),
- L4 L- Y9 U" c M$ x .ena(ena), # v! ?) i3 {' o- ?
.set(set), : J- Y, W _% w j9 w; [# f
.outp(outp); x% B j0 ]( M I* q
);
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. W8 a& ]; m( L% \! b, s initial begin* s F: ~/ e Y
sclk = 0;
3 e* q9 K* O1 G ena = 0;/ [1 B) U- S4 f5 D) @5 \- K
set = 0;3 F/ [- v; A& \* r' P
end
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( w+ j* b7 {, A* Z5 N2 w) s: qalways# 5 sclk = !sclk;9 h( Q* {* k& k% H
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initial begin
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ena = 1;8 |+ b! q* G, k3 p9 v
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set = 2;% ~" _ P. @' V) I& k2 U! x: y
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set = 3;( h* T3 L5 e$ i, \. h. Z6 Z9 f0 }
#20007 @1 k2 @2 p# f0 d5 K7 d5 m
$finish;/ e$ l4 V% s; j& O. w$ N
end
* d* o. B) X$ ~' s5 Bendmodule // xclk_tf |
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