|
0. Check circuit topology and connectivity.! ^4 E7 c2 ^8 L8 J, g. t7 e
This item is the same as item 0 in the DC analysis.7 _* \' y2 | y% V! }5 q
+ ^: w! Q3 D1 S, t) V( b1. Set RELTOL=.01 in the .OPTIONS statement.( |3 S# g+ E' w
Example: .OPTIONS RELTOL=.01
5 ^2 j4 a; _( _
: |2 a2 H% M2 F! i2. Reduce the accuracy of ABSTOL/VNTOL if current/voltage levels allow it.2 O/ n% {9 o% ?. c$ ]
Example: . OPTION ABSTOL=1N VNTOL=1M
t) e* P! f& ~! v, F' h/ {. y5 J
6 \ Q# V+ C) ~: S3. Set ITL4=500 in the .OPTIONS statement.- [& j) C1 \# \$ G+ W8 Y9 ?
Example: .OPTIONS ITL4=500
! N9 q9 a( Y* v# I" M/ K9 \+ v
/ Y( Q+ T' q% g. K' U4. Realistically Model Your Circuit; add parasitics, especially stray/junction capacitance.& p& L7 I) O7 ~& j( L0 X
# D% P) D( \1 L: T8 V, U% j5. Reduce the rise/fall times of the PULSE sources." e0 e+ {$ ^7 ]2 \9 \5 F
Example: VCC 1 0 PULSE 0 1 0 0 02 e( ~8 s- ~& _ e2 D* n
becomes VCC 1 0 PULSE 0 1 0 1U 1U
, |3 P% d' |9 o# N& K1 D
: k l u7 k2 B- m6. Use the .OPTIONS RAMPTIME=xxx statement to ramp up all of the sources.
/ s, I1 L3 |7 S- R! y& P1 BExample: .OPTIONS RAMPTIME=10NS
0 \' j- V; c: h% o) R& ^6 \" E8 [ [7 u: {; K
7. Add UIC (Use Initial Conditions) to the .TRAN line.2 G: x! ?! j, P6 ?4 N9 m
Example: .TRAN .1N 100N UIC6 R' @- a! T9 c+ J+ x5 h% o" o1 e0 h2 s# j
: U2 q: o5 L B1 i' j8. Change the integration method to Gear (See also Special Cases below).
& d% M7 i, z: l, ~$ mExample: .OPTIONS METHOD=GEAR |
|