IP development & verification engineer/AM 請進來交流最難職位任職要求！

tk02561

招聘公司：A famous IC company
工作地點：Chengdu
6 V5 Q) X0 D$ h% Z& o* X
. B/ C' k, p3 E) N' w崗位職責描述：
1. IP整合，合成，驗證和修正；
8 u8 y; J6 t8 t% v' s2. FPGA平臺的搭建及基於FPGA的系統驗證；

+ c+ r) V8 s- C  C0 X# y職位任職要求：
1. 微電子/電子工程或相關專業本科、碩士及以上學歷;
3 Q" w5 M  l( K8 K  E' X2. 良好的數位電路設計及模擬技能;
3. 有在FPGA上通過Verilog語言開發及驗證IP的經驗;
4. 有digital video processing(數位視訊處理) IP開發及驗證經驗者優先;
: h% q3 D0 a3 J5. 有C/C++/Matlab設計技能者優先。

ranica

招聘公司：A famous IC company
招聘岗位：VLSI Sr SOC Engineer
1 x1 c, Q9 A  B! M% Y5 I7 L( L工作地点：shanghai

, f# Z" p' V+ v. W岗位描述：Job Responsibilities:
  [7 _2 c! h& b3 {' _; HReporting to the SoC manager, the candidate is expected to be responsible for following tasks:
- Develop state of art 45nm complex media processor SoC products with embedded cpu, memory controller, media processor and various mixed signal IPs
  l$ l; {2 h" b- Work with other cross functional teams in China and overseas to specify, design, validate and improve SoC quality and timeliness to production
- Participate in SoC architecture definition, SoC integration and verification
- Create and optimize DFT structure, STA constraints, pad & package selection
+ V' q/ g9 j* S8 D- Work with physical design team to ensure a successfully implementation until tape-out by performing RTL rule check, LEC and power analysis etc
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( k, i! ^% G; L3 V4 Z5 C" a, i职位要求：Job Requirements:
& B% T1 H) Q4 D2 T( [+ \% w+ Bachelor degree in Electrical Engineering or related area, MSEE is preferred.
+ 3 years or above experience in ASIC/complex SoC design or verification.
+ Familiar with hardware description languages such as Verilog, System Verilog and VHDL
+ i  N8 F, j% \0 \& P' A. y5 A+ Knowledge of script language, such as Tcl, Python, Perl are required
+ Familiar with IC design & verification tool flow with hands-on experience in DC, PT, NC-Sim and/or Spyglass
8 N9 x; ^8 O1 o6 E' E+ c8 \3 S% E; e+ Good English and communication skills; will need frequent communication with foreign team.
- k; ?- e: r! i6 g+ Experience related to video/audio decoding, process technology and reliability qualification is a plus

ranica

招聘公司：A famous IC company
招聘岗位：Sr. Audio Design Engineer-DFT
' x0 A6 c' t; q6 f3 J工作地点：shanghai
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3 u3 H4 y4 \0 O; N! G岗位描述：
7 h, r+ p# d0 v, Z# ]1.Toplevel integration and verification of IP deliveries
2.interact closely with the Audio IP team (Freiburg, Germany)
6 {- Z8 P% V6 e  m( A9 A3.Support DfT team during integration
4.Support Test Program Development
& d8 C- L  B6 f% y+ h5.Support frontend and backend team through the whole design flow until tapeout (in Freiburg, Germany and in Shanghai)

职位要求：
Qualifications: (Education, Experience, etc.)
1.Bachelors/Masters degree in Engineering (Electronic Engineering) or equivalent
/ [& @: h% v% f' z" f4 T  z; R2.Experience in standard EDA Tools and Methods (Design Compiler, RTL Compiler, Primetime etc.)
3.Experience in RTL coding (Verilog) and verification
7 U& K8 {8 _. y( x( v4.Experince with structural test (Scan, MBIST)
" w% ^3 y, R- h8 }  E' \& [5.Candidate must be able to work independently and interface with various groups
1 K% }$ T! M: {7 Z6.Spoken language: English fluent
8 q8 P8 o. U& U  O4 F0 ?7.Ability and will to travel

ranica

招聘公司：A famous IC company
招聘岗位：(Sr.)IC DE(DAV)
% G5 H7 ?4 L4 G/ }" j- c工作地点：chengdu
6 E0 A' B) e. }. \" h( e* q
# u8 ~5 [, }- W4 `岗位职责：
1. LSI的逻辑电路设计;
. h/ w0 ~% y  h/ C* Z2. IP整合，合成，验证和修正；
3. 综合、静态时序分析；
+ h1 ]( D( c8 O& b) @+ j4. FPGA平台的搭建及基于FPGA的系统验证；
5. 系统整体验证及调试，芯片的测试等。
' ?% |/ m1 {* O/ M8 M+ P. {
职位要求：
1. 微电子/电机/电子工程或相关专业本科、硕士及以上学历;
& ~- v) ?, c, k) K2. 3年或7年以上IC设计工作经验，具有视频，通讯等芯片设计经验；作为Leader开发过一个项目者更佳;
3. 熟悉数字电路正向设计，包括Verilog-HDL硬件描述、综合、仿真等;
6 R6 r/ _$ w2 n) e( h4. 熟悉C语言编程；
5 ^8 Z$ [& @5 @/ b0 f1 |5. 能熟练使用Xilinx与Altera FPGA开发工具;
. E% {0 g9 ?/ ]1 n% O* ?' L6. 熟悉逻辑综合，时序分析，Verilog仿真等IC开发环境。

ranica

招聘公司：A famous IC company
招聘岗位：ASIC Engineer of SOC and Video system
工作地点：shanghai

岗位描述：Responsibilities:
" r. w, B% t+ {$ F+ ?- SOC design
SOC methodology define and control
  R4 y9 k: t$ U* X# R! q/ A) oLead and audit block level synthesis and timing closure
, h. X' d. p. i% H4 B! gTop level synthesis
Top level STA (define SDC and be responsible to timing signoff)
, n* v* F7 V# q8 |Understand DFT flow, can do necessary support
- Video design
$ @8 Z3 v* y0 k9 W- H6 fIP level Micro-architecture, RTL Design, Verification, Synthesis and timing closure.
# U6 ]( v0 V5 n$ V) T; TSolid knowledge and experience on video block design and debug
Top level architecture, including clock/reset structure, address mapping, bandwidth analysis, etc
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职位要求：
7 ]: [0 w% q4 p$ ~: k- QMust have:
/ u1 t4 C: g) }+ ~% P9 \, rBSEE Degree or above
: m) O$ V& g/ u5 J4 p3 or 5 years of experience in ASIC design
Familiar with industry synthesis/STA/formal tools
Familiar with at least one of script language such as perl/tcl/shell
. N! C+ q, L* P  M! s& zSolid RTL design experience, better in video system
0 L" m8 f" [, n" |  {Self-motivated in solving problems
Good communication skills and fluent in English.
Good team player.

ranica

招聘公司：A famous IC company
6 |2 H4 e' j1 J0 W6 O5 ^招聘岗位：IC Logic Design Engineer (Video R&D)
6 V2 b3 |6 f( J7 R: b工作地点：Shanghai

" t# Y8 C4 t6 p$ j岗位描述Job Duties:

- j$ M0 ^7 u) \* i  c% P· IC logic design (Front End) for Video Quality Processing ICs or SOCs (System on Chip), including Video Algorihm development Verilog RTL coding, Syathesis, StatiTiming Analysis, Integration and Verification, FPGA emulation adn C/C++ Modeling.
5 m: p( \/ p0 X, E# _# U3 }
( x# d$ Y1 q9 {( }# i0 G职位要求Qualifications:

6 t( V5 S2 O& Z1 ]* v· Education: Major in EE or related, Master or above.
, E6 l/ N7 Y3 Z( k3 F· Familiar with EE logic design flow, such as RTL coding, simulation and synthesis.
: C+ Q: w% u: h3 u: A' r1 f7 R· Can write C mode and RTL to implement algorithms.
, H& K+ l) D1 F, K· Working experience preferred, but not a must.
/ O) x  F. P: E  f1 ?7 ~· Familiar with TV system and video processing algorithms is preferred, but not must.
· Good personal characteristics as an employee good communication ability and co-work sprit

ranica

招聘公司：A famous IC company
, ~! R+ d  H# P* M招聘岗位：Senior IC Physical Integration Engineer
工作地点：Shanghai

3 m/ j& R9 [" M4 x* U% K岗位描述Job Duties:
1. To execute circuit and final physical implementation related technical tasks in projects including, but not limited to IP ownership and integration, ASIC physical systems and circuit implementation, ASIC characteristics verification and validation and device interconnect verification.
6 `$ n: a' c1 m: z
职位要求Qualifications:
1. Bachelor / Master degree or above.
; X( O# r- {/ @9 C* K3 n2. 5+ years experience on physical implementation and circuit design.

ranica

招聘公司：A famous IC company
招聘岗位：ASIC CAD Engineer
- O$ f, ^, _4 @" `, [$ K工作地点：Shanghai

岗位描述Description of the Role / Responsibilities:

% b& E* ^8 E7 N% u2 J; cParticipate in the design and implementation of the leading edge ASIC chip.
1 E, `: q9 `, d) M6 N$ }Your focus is on design flow
$ @1 |3 A9 n- E7 ?/ a! c" Z( D7 ]# a% R) DEnsure the design methodology correct and improve automation and productivity. The main flow steps include:
FE: Synthesis, Simulation, STA, Design Check and memory compiler etc.
  U% C- m2 j& N! z% d' t, ABE: Place and Routing, Physical verification, Signal integrity, Power analysis etc.
4 c3 s1 S+ n1 }( {Another important part of the job is doing support to FE /BE team.
  P& t& N" T8 t! rWhen they have a real design issue and can’t solved by themselves, you may be asked to jump in for debug and find a solution. Usually you will work with EDA vendors on such case.
Responsibilities besides support project work also include interfacing with other implementation experts across different development locations, and driving the continuous improvement of advanced implementation methods to Trident digital TV and Set-Top-Box projects teams.
3 O. d7 V. ~) I
职位要求Experience and Skills Required:
; z" `4 ^( W5 Q5 C1 F# ?Essential
Major in Electronic Engineering or Computer Science.
) p8 s8 f$ Z5 R# g' x/ ^! DMaster (or Bachelor 2+ years related experience)
/ e& N% a/ L& j" ?Strong programming skill with one or more following items( Perl,Tcl, C/C++ etc).
Experience with industry standard development EDA tools and flow.
FE engineer: DC, RTL Compiler, PT, Conformal LEC, NC. VCS
- h2 R( t' t; b% d% n2 hBE engineer: SOC encounter, Apache Redhawk etc.
Good written and fluent oral English.
Good communication skills and team work.
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+ Y) W# w6 }6 u! @7 V( G' y( HDesirable
* i1 k" s; e( _6 p+ rReal ASIC project experience as a FE or BE designer is a plus.

ranica

招聘公司：a top 15 semiconductor company
! Y3 U1 K% N( [0 z* W' D0 G! d8 N招聘岗位：System Engineer
; f- g- o) f) M% ?工作地点：Beijing
" J) s/ [/ X& @
8 L. K; H4 T- z! q) N# w- d岗位描述：
6 }0 u! |" q) A6 P4 m, C" ?Responsibility: - Develop reference platform for image processing with XX products and third party IP/products. - Work closely with AE on demonstration system for XX customers. - Develop full functional reference platform for image processing - Deliver image processing reference platform user manual and related documentation. - Develop relationships with IP provider. - Deliver image processing reference platform training.

+ N1 {- v- e8 v0 k8 N( ^5 U职位要求：
Requirement: - MS in EE/CS. - 3 year+ experience for MSEE and 1 year+ for PHD. - Strong FPGA and Embedded firmware experience and skill - Strong background and experiences of system design in both hardware and software level - Strong background and experiences of image signal processing is preferred. - Strong background and experiences of PCB board design is preferred. - Good spoken and written English - Ability to work independently with multiple teams to meet complex objectives - Self motivation, good team player and good communication skills

ranica

招聘公司：A famous IC company
" s" \" I2 E7 s3 {招聘岗位：Software Developer – SPICE Netlist Parsing
, }8 E3 y+ S7 g工作地点：Shanghai

, U1 L/ M, Z; G6 U% m. c( ^岗位描述：
Job Description Develop and maintain the SPICE netlist parser for IC-Package-PCB co-analysis
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6 i- B  o, a( ?. b/ \! v职位要求：
Qualifications Strong knowledge of Lex&Yacc, C/C++ programming skills Experience with the algorithm and implementation of large data parsing, handling and processing Experience with SPICE simulation is a plus Good communication (written and verbal) skills in English BS, M.S. in Computer Science or other related areas

ranica

聘公司：A famous IC company
招聘岗位：Software Development Engineer
工作地点：Shanghai

岗位描述：
, a0 X3 U1 ^4 \! h" S7 ^' BResponsibilities: Develop application software tools to enable Application Engineers and IC design house, foundry, OSAT customers to do test program conversion, development and optimization on V93K platforms. Develop production solutions for XX customers to improve their production efficiency. Develop conversion and other productivity tools to improve Application Engineers’ efficiency, make the tool as generic as possible and reusable. Work with cross functional teams to collect and understand internal and external customer requirements. Do solution architecture design of complex software solutions. Do software coding, following with SW development process. Contribute idea to improve the effectiveness of the SW team and Application development center.

7 F+ l2 W( Z4 A. g# Y- ]0 a4 @8 ]职位要求：
0 g3 ?+ m: K# k2 V/ fQualification (Must): 1. Bachelor degree in computer science or related 2. 5+ years experience in software development 3. Excellent programming skills in Eclipse or Java 4. Strong C/C++ programming skill 5. Strong knowledge of software design & development methodologies such as , OOD & OOP, design pattern 6. Familiar with iterative development method 7. Familiar with Linux platform software development 8. Positive attitude and good communication skills, good team player 9. Strong verbal and written English skill 10. Basic knowledge on electrical engineering 11. High Passion; A quick learner under heavy pressure 12. Flexibility to travel internationally Desired: 1. Master degree 2. Knowledge in semiconductor test systems 3. Experienced in product development 4. Perl programming skill 5. Good project management skill

ranica

招聘公司：A famous IC company
7 L3 E# ?' ~# |4 R招聘岗位：Engineer, Technical Lead Software
8 y( k" I8 ]0 f$ U* A, V2 r工作地点：Shanghai

岗位描述：
* w# u( A$ L  O$ Z# N7 ?Job Function Design and develop software and firmware for ABU SOCs. Performing customer support job functions.
- x- z6 W  o4 i% w9 Z. w9 ]
5 R; p; S1 S" s: S" a* `9 b# h职位要求：
Skills/Experience - 4+ years in embedded firmware development - experience in networking protocols - experience in C and Linux programming - good knowledge in RTOS Responsibilities Education Requirements - Master in EE or CS.

ranica

招聘公司：A famous IC company
! L1 }' {. Z+ _8 y, e招聘岗位：Program Manager
工作地点：Shanghai
3 [7 c  i4 J. ?* c8 }0 p% g
  f! Z  k1 g, w$ b岗位描述：
/ X' x, {! v4 KJob Description (tasks and responsibilities): The Program Manager will manage cross-functional teams in China and headquarters to complete the semiconductor IP and product development from concept to releasing it to production. Responsibilities will include: • Overall responsible for managing semiconductor IP and product development from concept to releasing it to production • Follow product life cycle management framework to carry out development • Form IP and product development teams including digital design, analog design, systems/validation, SW engineers and QA engineers • Complete detailed development plans including cost & ROI analysis, identify & mitigate risks, and carry out reviews • Interface with Marketing and Sales to ensure that product deliverables are identified and agreed to • Manage all the activities of IP and product development teams • Report status of the project on the weekly basis • Address customer issues related to the IP and product • Provide leadership in product development and technology competency

职位要求：
& t# Y0 g4 y4 h- p) Z2 ?3 E6 L- vJob Requirements (education and experience): • 10+ years of experience designing and implementing video/image processing semiconductor IPs and products, with at least 5 years program management experience and exposure to the full development lifecycle • In-depth knowledge of video codec (MPEG2/4, H.264, AVS ) and image singal processing • Track record of having delivered complex IPs and products from concept to production • Proven experience in managing cross-functional development teams • Proven experience in developing consumer electronics products and supporting global customers • Excellent organizational, leadership, decision making, human relations and written and oral communications skills • Detail oriented and sound judgment on technical matters as well as team dynamics

ranica

招聘公司：A famous IC company
( p' }# J# A* c9 J* e1 v招聘岗位：Sr digital design engineer
) k7 Y2 m' d$ i/ z9 r) |, Z工作地点：Suzhou
7 Z( `/ u9 n, U$ U  x/ Q+ q$ p8 y
7 w8 I7 X- b& w, n: c% D5 q岗位描述：
岗位职责描述带领团队完成functional block划分与设计。 数字电路芯片和模块的规格制定 用Verilog语言实现电路功能，仿真并验证电路的功能 对模块进行综合，并分析时序 分析代码覆盖率
0 G6 D2 {- @2 U1 L5 o  l
职位要求：
任职要求基本条件 ¬--本科及以上学历，五年以上相关工作经验，有闪存控制器经验优先。 知识技能 --了解IC 设计流程； --熟悉architecture定义，能够划分合理的功能模块； --具备RTL设计经验，逻辑思维严密； --具有良好的debug能力和问题定义的能力； --ARM相关芯片的开发流程

ranica

招聘公司：A famous IC company
招聘岗位：数字前端实现工程师
9 h# k/ y5 o8 q( @工作地点：Beijing

岗位描述：
) u" h+ O* h* r职责： 负责芯片的逻辑综合，从RTL到Netlist的实现。 参与部分DFT工作。 负责SDC检查维护，前后端设计沟通，。
: @5 I' P) B# E- x" e1 S1 _
职位要求：
要求： 精通DC,PT，熟悉Verilog，SDC。 有过实际TAPEOUT经验,两年以上工作经验。 有DFT工作经验者更佳，对后端流程有一定了解。 具备团队合作精神和责任心。

ranica

招聘公司：A famous IC company
( _! w2 `, t5 e: o' e8 V招聘岗位：数字前端实现工程师
工作地点：Beijing

岗位描述：
职责： 负责芯片的逻辑综合，从RTL到Netlist的实现。 参与部分DFT工作。 负责SDC检查维护，前后端设计沟通，。
( m! d" s$ _, n
职位要求：
" C- y7 M* T2 R" o3 P5 @要求： 精通DC,PT，熟悉Verilog，SDC。 有过实际TAPEOUT经验,两年以上工作经验。 有DFT工作经验者更佳，对后端流程有一定了解。 具备团队合作精神和责任心。

ranica

招聘公司：A famous IC company
7 O; H/ R) K& I5 P4 q  N# k招聘岗位：Senior / Staff ASIC DFT engineer (MCE ASIC)
6 ]2 Z5 ]) T) }" y7 A; a工作地点：Shanghai
/ S9 z& z) y( n! y! Z
岗位描述：
$ R' k2 e2 ~  s0 p  UDescription: Sr. / Staff ASIC DFT design engineer Focus on DFT design & debugging of leading-edge large SoC.
8 p" V8 A% D5 x( T
: L& C6 ]2 O. s. _7 `职位要求：
- f. |$ s) q0 V' H2 g% \6 XQualifications: 1. BS (MS preferred) in microelectronics, electrical engineering or equivalent with 3+ years of DFT design experience, preferably with large SoC chips. 2. Handy experience on scan, mbist, boundary scan, ATPG and analog DFT, with Mentor/Synopsys/Syntest tools and RTL/gate simulation. 3. RTL design and STA experience is a strong plus. 4. ATE tester experience is a plus. 5. Must be able to communicate in both written and spoken English 6. Good team work spirit and communication skill.

ranica

招聘公司：A famous IC company
招聘岗位：Senior / Design Engineer ( Flash IP)
工作地点：Shanghai

6 B0 l( c" F: `8 G8 O) j# b岗位描述：
Job Description and Responsibilities: -Design and maintain Flash memory IPs; -Support user / customer to use XX embedded flash IP.
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职位要求：
6 e: n& c6 J" `2 X6 w: {) ~Key Competency Requirements: -Technical knowledge in IC design methodology; -Experience of non-volatile / flash memory, MCU analog IP design a definite advantage; -Knowledge of Verilog, Synopsys synthesis / simulation tools, HSPICE, Cadence Design Entry, IC layout tools, Dracula, Silicon Ensemble or other equivalent tools. Education and Experience Required: -Bachelor degree or above in EE; -More than 2 years of analog design experience; -Preferred:Some Analog/Layout design related experience; Some Process/Technology related experience.

ranica

招聘公司：A famous IC company
招聘岗位：DFT team manager (MCE ASIC)
- x. \3 ^" ^" K" _8 g工作地点：Shanghai
! E9 g, h6 ?9 u
4 J# L1 P$ z4 y岗位描述：
Qualifications: 1. BS (MS preferred) in microelectronics, electrical engineering or equivalent with 5+ years of DFT design experience, preferably with large SoC chips. 2. Handy experience on scan, mbist, boundary scan, ATPG and analog DFT, with Mentor/Synopsys/Syntest tools and RTL/gate simulation. 3. Good communication skill in a multi-national multi-team working environment. Experience with ATE tester and Production Engineer is a strong plus. 4. RTL design and STA experience is a strong plus. 5. Fluent in both written and spoken English
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职位要求：
: Z$ }* i8 i1 ~. VDescription: DFT team manager Focus on leading the DFT team for DFT design & debugging of leading-edge large SoC, and work with Production Engineering team on large volume production.

ranica

招聘公司：A famous European IC company
! U7 W0 l+ S( ?: y0 I2 F! V& U0 ~! [招聘岗位：Senior Digital Design Engineer
# O8 a. [! a6 p9 e工作地点：Shanghai
0 I' H" j" y9 {8 _
/ O/ o3 [' [# J0 ~$ }  ?) @, ]岗位描述：
- Define specifications in cooperation with international teams - Design and verify digital circuits for mixed-signal application - FPGA-based verification of digital circuits - Estimation of efforts and schedules for design projects - Close cooperation and interaction with international teams

. k6 `0 k; a" d职位要求：
Requirements: - Bachelor or master degree in Electronics, Communications, - Computer Engineering or equivalent, 2+ years - Strong background in digital design and verification - Experience in working with FPGAs - Flexibility and open-mindedness; Self motivated, excellent communication skills and a real team player - English written and verbal; - Willingness to work and interact in international teams