FPGA verification Engineer most difficult job functions?

ranica

招聘公司：A fabless IC design company
+ P% T$ n2 w7 l' ?" Z8 p2 \( q/ T招聘岗位：系统产品经理
工作地点：Beijing
# l1 B7 ~! ]! J+ C$ M" E
岗位描述：
" e% s9 J* ^$ L/ W主要职责： 定制芯片的实际应用方案，为客户提供具体系统应用的解决方案，统计芯片在应用中出现的问题并形成改进建议书。
- Q( Z/ B- h, g  t& d
职位要求：
职位需求： 1. 计算机、通信、电子工程类专业，本科及以上学历。英语CET-4级以上水平，良好的英文读写能力； 2.了解民用消费类产品的框架结构及应用领域； 3. 具备较强的芯片级理解能力，对高速视频接口（LVDS, DVI, HDMI, DP）、数字电视相关芯片有深入的研究或应用，可以很准确的知道芯片的指标含 义和解释； 4. 熟练掌握 Cadence或PowerPCB/Powerlog ic等软件，熟知原理图设计，PCB 的布线规则和产品的生产流程。能够独立调试系统板级硬件； 5. 具备敏锐和快速的反应能力；良好的思维能力、信息收集、分析能力； 6. 良好的团队合作意识和沟通能力； 7. 适应经常出差，勤奋刻苦，爱岗敬业； 8. 具有较强的嵌入式软件编程能力，熟悉LINUX系统的应用。能够独立调试系统系统软件； 9. 具有产品应用及管理经历者优先。

ranica

招聘公司：A famous IC company
+ r: e% S2 ^" d: F& d- g& F  w招聘岗位：SoC System Verification Engineer
( j. v6 y: w% m- H6 i工作地点：Xi'an

. m5 f2 [. Y) |岗位描述：
Job Description: * Defines and develops system validation environment and test suites. * Hardware System Validation of Baseband ICs and peripheral for Mobile Terminals Technical coordination possible depending on experience and skills * Functional verification of the baseband IC and analyze of the occurring problems * Definition and implementation of test cases for the different modules(HW/SW, Low level drivers, Linux drivers) * Lead internal customer support during the evaluation phase * Interface to Concept Engineering Team, Design Team, SW Team

ranica

职位要求：
$ X% ~$ i; w# i$ C: c  CJob Description: * BS. or MS. Degree, MS. preferred, in Electrical / Electronics Engineering or equivalent * Minimum 2 years experience with the following tools/domains are recommended: * Knowledge of Embedded system * ARM Tools (ADS), GCC know how * Script languages (GNU Make, Make, Make File structures) * Debug Tooling Multi-ICE, Lauterbach, OS-aware debugging * RTOS Symbian, Nucleus, Linux or equivalent * Usage of C models (Virtual Prototype) to test Software before silicon availability * Configuration Management (Versioning Tools: ClearCase) * Knowledge of the following cores/architecture concepts are recommended: * ARM 7/9/11/Cortex Series and all controller functions: Interrupt/DMA... * Multimedia concept: JPEG, MPEG, Camera, Display, Multimedia Card Storage devices... * Standard Interfaces (UART, SSC, I2C, USB HS, USB FS, USB HSIC, MIPI HSl, SlimBus, MIPI Unipro¿) * Memory devices (DDR1, DDR2, SDRAM, Mobile RAM, NAND and NOR Flash) * Connectivity functions: WLAN, BlueTooth, GPS, FMR... * Good English, Excellent communication skill and team spirit oriented

ranica

招聘公司：A famous IC company
' D- q  s' r  I- U; W  i5 z' S招聘岗位：Digital Design Engineer
工作地点：Beijing
1 I% L: ?# _2 g1 P3 {& {/ ?! f
) X/ H. c1 n9 R4 Z+ X岗位描述：
2 ~- F) n# `% A' W, e% B! jDuties · Digital design, including synthesis, timing simulations, power optimization, DFT · Mixed signal design; and verification · Define, develop, and implement characterization, test plans, test vector generation · Work with other division test groups inside/outside FSC to identify possible co-operative opportunities to optimize test solution · Work on the design of analog blocks like voltage regulators, I/O buffer, output drivers, voltage references, oscillators · Work with product definition; characterization, and test engineers in the full product development flow; Work with application & test engineers to define optimal design and characterization solutions, based on design objectives · Layout floor planning, including P&R, DRC, LVS, and LPE
% m2 \: B8 m& D/ P
职位要求：
& C9 {4 E8 h, L& d0 SRequirements · Minimum 3 years direct digital IC design experience · Minimum 3-5 years direct mixed signal IC design experience · CMOS mixed signal circuit design and proficiency with industry standard design tools and Verilog/VHDL · Knowledge in CMOS/BiCMOS Analog circuit design Experience in Cadence IC Design tool set, simulation, verification · Matlab/Simulink/VerilogA or other behavioral simulation expertise a plus Team-based, cross-functional organizational structure experience preferred · Excellent written and oral communication and presentation skills · Satisfactory written and oral communication skills in English · MSEE degree or above or equivalent experience · Strong communications skills; written, verbal, presentation and listening; · Good interpersonal skills to work in a team environment; · Good command of written and spoken English required; · Excellent interpersonal, written communication and presentation skills

ranica

招聘公司：A famous IC company
招聘岗位：Sr. Design Engineer
' ~( i/ b4 D* w' H. z工作地点：Shanghai、Beijing
$ Q: \# \, D  R7 k- b
岗位描述：
Duties · Analog IC circuit design, simulation and verification · Design analog products and blocks such as high current or high capacitive load output drivers, operational amplifier, comparator, voltage reference, oscillator, error amplifier, voltage regulator etc. · Design of the switching power IC, DC-DC converters, for mobile/portal application · Evaluation, simulation and analysis of power architectures and circuit topologies · IC layout including floor planning, DRC, LVS, and LPE · Work with application and testing engineers to define optimal characterization and testing solution · Work with product definers and product engineers in full product development flow
" i+ |. [5 {+ k
职位要求：
2 q; T% w# R9 ^: u6 iRequirements · Minimum 5 years direct DC-DC IC design experience, with MSEE or above degree · Strong knowledge in analog CMOS and Bipolar IC design · Working direct experience with switching power supplies, DC-DC converters, Battery charger, and their various topologies · Theoretical understanding of the power electronics, switching power supply topologies · Prior experience with power management related IC design a strong plus · Knowledge in analog IC layout · Matlab/Simulink/VerilogA or other behavioral simulation expertise a plus · Excellent written and oral communication and presentation skills · Satisfactory written and oral communication skills in English · MSEE degree or above or equivalent experience · Strong communications skills; written, verbal, presentation and listening; · Good interpersonal skills to work in a team environment; · Good command of written and spoken English required; · Excellent interpersonal, written communication and presentation skills

ranica

招聘公司：a top 15 semiconductor company
招聘岗位：Product Engineer
工作地点：Beijing
  Z9 B# x7 M4 ~' R
" G, K1 m! Z, g% @1 O4 E) W" O岗位描述：
- Design database verification by simulation and on FPGA - Chip function evaluation - Develop test firmware and tools (Hardware and Software) - Develop evaluation board - Cooperate to debug chip issues - Customer support • Assist with customers’ issues • Visit customers and provide on-site support • Build up demo system
! Z' p* R: [+ C/ f, o$ ^# n; s
# d- X. {* j) `5 ]. ^# X1 C" n3 G职位要求：
- BSEE or above with minimum 3 years communication system experience - Familiar with Verilog. Has digital design experience with Verilog in real project - Minimum 3 years FPGA working experience, including code writing, timing analysis, debug - Familiar with at least one of schematic and PCB layout tools - Excellent English skill will be required. - Strong inter-personal, teamwork and communicational skills

ranica

客户 A famous IC company
% N" \: z; Y' W$ ]6 o2 P5 t2 i  A% g地点 Shanghai
! b' j5 Y+ O3 h) `3 q- |
职位描述
- r$ f3 X& f0 q7 jWe are looking for a person to join a design team to execute a state-of-the-art IC design project in the wireless communication field. Candidate must be familiar with digital IC design flow with a proven record of design and verification of a complex design project that led to successful silicon. Proficiency in Verilog is required.
/ M7 S- P8 F1 w* i' y1 w* r* K
职位要求
Experience in the following areas of expertise is desired:
) T! t8 R5 |9 h# X$ cWireless media access control (MAC) design experience would be highly desirable
Knowledge of TCP/IP and DMA Offload Engine design experience will be a plus
5 ]8 n# s! A7 _8 ]( g) P9 ]+ ZRTL design, verification, and chip integration
. k9 _. p# D2 X) j# A6 {' LExperience in the following is beneficial but not necessary requirement:
Communication systems and RF systems
Familiarity with wireless communication systems and standards (802.11b/g/n and WiGig)
Knowledge of interface protocols such as PCI/PCIe would be a plus
FPGA design flow, testing, and emulation bringup

Other requirements:
% x* p) O8 p- \- w! |; {& lFamiliar with design and verification languages, EDA tools and ASIC/SOC design methodology
; l& M! H* ]$ D+ pGood script language skill, such as Perl, Tcl and Shell
Good written and oral communication skills in English
Good Team player
7 u/ ^. g* Y; r/ k" n9 Y6 xCandidates must have MSEE degree with at least 5 years of experience

ranica

招聘公司：A famous IC company
招聘岗位：高级ASIC设计工程师
工作地点：Shanghai
* }3 V. F; j2 x  K; a( Z( K
; z: e4 F( u/ G) I岗位描述：
& K% O$ s. q8 E8 I/ Q1、定义设计模块结构并编写芯片设计规范； 2、使用VHDL/Verilog编写逻辑模块的RTL代码； 3、编写测试向量对模块进行仿真验证； 4、在FPGA平台上进行芯片级的测试验证； 5、进行模块级的芯片综合与时序分析； 6、编写完整的设计和验证报告。

职位要求：
9 h0 F% `8 Z: s: y1、具有电子或通信工程类硕士以上学历； 2、 熟练运用Verilog/VHDL进行芯片前端设计，熟练运用设计仿真综合和测试工具，如quartus，Xilinx，modelsim，nc，debussy，逻辑分析仪，信道仿真设备等； 3、深刻理解数字电路设计和时序分析方法，并拥有故障定位和解决问题的能力； 4、深刻理解通信原理、数字信号处理等基础知识，熟悉无线通信原理与常用算法； 5、具有3年以上芯片设计经验，拥有无线通信物理层开发项目（如DTMB、CMMB、DVB、3G, LTE等）经验者优先； 6、工作认真严谨，积极上进； 7、良好的团队合作意识和沟通能力。

ranica

Verification Engineer

公      司：A famous IC company
工作地点：上海

; }7 n- T5 V' H, |The Role:
·         ASIC  verification
·         Work closely with the California teams
/ F1 b3 T5 }3 u·         Support chip tape out and bring up
# ]9 I% S8 f$ ?& p/ `  }" o" n1 _
+ t( E: l# d- n: ARequirements:
·         3+ years experience in ASIC Verification
·         BS in Electrical Engineering (or equivalent) is a must have, MSEE is desired
% E# i8 I" L3 [- t$ y" E·         System on Chip (SOC) Verification Experience, including AHB/AXI, CPU, Interface integration verification
4 U3 ]7 ]) P4 I  [5 C5 {$ }·         Very familiar with verification languages – Verilog, System-Verilog, and VMM
·         Test plan and test case documentation
·         Functional coverage and code coverage analysis
·         Must be familiar with various scripting languages used in verification, including Perl, Csh, Make, etc.
0 T0 Y4 K. X5 s9 D" f! D% z3 Q) y* e·         Experience verifying interfaces such as PCIe, Ethernet, DDR, USB
5 S) c3 U* X$ J8 @·         Working knowledge of networking protocols 802.3 and 802.11, especially Medium Access Control and TCP/IP
  E$ a) I' B. y, v3 C$ r: c·         Working knowledge of C programming language
·         Must be familiar with the ASIC verification flow from feature identification to test bench development and through final tape out sign-off
% r# c7 t, ?  O* f+ N  i·         FPGA emulation experience a plus
·         Chip bring-up experience, including use of Logic Analyzer and Oscilloscope for debugging

ranica

ASIC Digital Verification Engineer
公      司：A mobile chipset semiconductor company
工作地点：上海

$ a) H& M. r! W8 O5 fResponsibilities:  
/ b4 Y6 {# o; L  |5 ^  Make verification plan for one module or whole chip.  
  Build up and maintain module-level and chip-level verification environment  
4 W/ o2 y- l4 `9 g7 T' v, y  Verify ASIC digital design based on case list, and output verification report.  
. `1 {" W0 V: D+ C$ Q  Also responsible for lint checking and formal verification.  

  @1 p4 L: I- W2 _. kQualifications:  
  Proficiency in logic verification.  
2 e/ P8 ]+ i/ X; G4 J: o2 ?  Experience with Verilog logic design language.  
  Experience with high-level verification languages such as System Verilog, System C, Vera or Specman e language.  
  Experience with UNIX/Linux simulation tools such as IUS or VCS.  
  Experience with C and C++ is a plus.  
+ E- r, @6 y6 t. ]; @  Experience with C_SHELL, TCL or PERL is a plus.  
  Experience with UVM, OVM or VMM is a plus.  
( r+ I) J: ^/ ?  g9 m8 l- M7 u  Good knowledge of SOC design is a plus.  
% e5 O* Z. X: b& F  Good knowledge of software design is a plus.  
  Self-motivated and good team player.  
6 Y- O! j8 {. O& I8 E1 p  MSEE or BSEE with 2+ years.

tk02561

Hardware Applications Engineer–Graphics
6 d0 \  U$ u6 M6 Z) k公      司：A famous IC company
工作地点：上海
) @7 J. R1 p/ L
Desirable
Strong understanding of microprocessors
, }: V" z- W  F- U. l/ ~A good understanding of the interaction between software and hardware
Understanding of FPGA or ASIC implementation flows (synthesis, scan insertion, layout)
C/C++, assembler coding or other programming skills.
Knowledge of GPU or graphics processing specification, like OpenGLES, Direct-X, is preferred

* d, N3 Z5 }% G% ~8 X; IJob Requirements：

tk02561

Education
Good university degree, in Computer Science or Electronics Engineering ideally, although other science graduates would be considered if they have relevant experience.
1 N5 V% R1 N$ |  
% Q' ]' w- o' g9 G8 ?: zExperience
* y) A) d" I' D* h" ]Minimum of 4 years industrial experience
7 v4 H" X' @+ H1 u. N2 VExperience or knowledge of FPGA or ASIC design, simulation and/or verification techniques, including RTL coding and simulation, in Verilog or VHDL
% X; S! {  D( B1 }5 j+ K, r- fExperience in integrating SoC peripherals
Experience of interacting with colleagues outside of China
Professional experience of customer and sales interaction
Demonstrable experience of problem solving and debug skills

* P/ L: Q' Y- D/ z: gPersonal Requirements
, K+ z8 ^# V8 Q. _Must have excellent written and verbal communication skills with both colleagues and customers, including good written and spoken English
0 a  K0 c, C5 k% wMust be proactive in obtaining engineering or management input, in order to complete project and internal tasks in a timely and accurate manner
Must have the desire and ability to solve problems quickly
Must be enthusiastic and well driven
Must be able to schedule own workload and plan tasks – based on both internal and customer requirements.  
$ C+ ]0 I& T% h8 kMust have good inter-personal skills, and be able to work well within a team; especially when under pressure
Must be willing to be flexible and accept new challenges
Must be able to travel on a regular basis, both to give customer training and also for internal business reasons.

ranica

Senior Digital Design Engineer
% o, J7 n' A3 ?; `6 d公      司：A leading semiconductor company
1 b  B* X( z4 B1 w6 v* C工作地点：香港
8 E9 ~7 U" ~$ l6 K8 g
Job Responsibilities:
1 ^4 _0 |$ A# H' [: g! Y- ?" r    Perform logic design, RTL coding, design verification, logic synthesis, DFT and static timing analysis
    Develop verification environment and coverage closure
, a' t( o6 }7 [( d2 ~) F5 `/ f. [    Support wafer level testing and silicon evaluation
+ ?2 q5 L0 p3 o) R+ |5 M/ P    Prepare technical documents
# H% M8 J* N9 b6 B& p, n
, u- [: U* q# N- U& T4 M5 gJob Requirements:
    B.Sc or above in Electronic Engineering or equivalent. Applicants with postgraduate degree would be considered as an advantage
2 s9 A3 B0 T5 B/ s    5 Years or above of solid experience in one or more of the following areas: Verilog-based logic design and synthesis, constrained random    testbench with System Verilog & UVM, assertion based design verification or circuit-level SPICE simulations
/ a% L) Q0 }4 Y0 [1 N    Knowledge of SoC and embedded system.
    Knowledge of scripting languages such as Perl, TCL and Make
$ ^. ]2 z( G$ ^$ e; ^* D9 Q    Candidate with less experience will be considered as Digital Design Engineer

ranica

数字IC验证工程师
公      司：A famous IC company
/ `2 ]  ?8 v; x7 d* a2 ]工作地点：上海

岗位职责：
- W1 F( G+ {+ z" j0 z1、负责整个团队验证平台的搭建、维护
2、先进验证方法和验证平台的评估、导入
3、各种IP的模块验证，SOC相关的集成验证、系统验证，负责验证计划的制定实施、测试用例的编写。
; P3 g; Z4 c* Y9 Q
# B8 X5 ^8 L7 s0 w# J职位要求：
6 p+ n: }; X' H/ j" d# \2 B1、大学本科及以上学历，电子、通信、计算机或微电子专业；
. c% H5 [* Y' F! E! V1 Y2、熟练掌握Verilog、SystemVerilog、C/C++等语言的编程，有扎实的数字电路基础；
3、熟悉SoC验证开发流程，了解常用的验证方法学，如VMM等；
3、有1~2年芯片验证的相关工作经验；
9 w) u: }1 J) I, \  U  C# C4、具有较强的学习能力、沟通能力和良好的团队合作精神；
5、有基于ARM处理器的SOC芯片验证经验者优先考虑。

jcase

数字IC验证工程师
公      司：A famous IC company
工作地点：上海

1 U' ^5 u" \  B岗位职责：
1、负责整个团队验证平台的搭建、维护
1 j9 a. Z4 V& D2 R4 d# n2、先进验证方法和验证平台的评估、导入
" L( L4 D6 ?* e8 r3、各种IP的模块验证，SOC相关的集成验证、系统验证，负责验证计划的制定实施、测试用例的编写。

" s: G- \& m& u" p9 x; u  Z职位要求：
1、大学本科及以上学历，电子、通信、计算机或微电子专业；
2、熟练掌握Verilog、SystemVerilog、C/C++等语言的编程，有扎实的数字电路基础；
3、熟悉SoC验证开发流程，了解常用的验证方法学，如VMM等；
3、有1~2年芯片验证的相关工作经验；
& U5 g- u! z, C7 f: K5 q& M1 c4、具有较强的学习能力、沟通能力和良好的团队合作精神；
9 D8 S8 y9 D: K3 o: b+ d* m5、有基于ARM处理器的SOC芯片验证经验者优先考虑。

ranica

Senior Digital Design Engineer
* w9 e4 a: b. b9 V8 O8 z- d公      司：A famous European IC company
工作地点：上海

! ^3 C) `! e6 g# V, c$ ~' A; IJob description  
- define system partitioning of s/c circuits and system  
7 l* s' M% r( g; n- define HW/SW co-partitioning  
- provide technical feasibilities based on system simulation and/or FPGA based demonstrator  
. D5 o3 ^3 Q7 `8 u$ v3 |0 i- propose new technical solutions on s/c and system level  
- Z9 b0 ]- Z# p. m% M0 y- design digital part of mixed signal (smart power) ASICs  
- close cooperation and interaction with international teams  
- coach junior engineers  
1 N7 }# g" K* t3 \2 L! T
$ m  z2 p, r) _5 cRequired knowledge competencies and attributes  
+ z- ~. a1 j$ n9 R* J, ^5 b- master degree in microelectronic circuits or systems, Communications, Computer Engineering (or equivalent)
- > 5ys experience in digital design  
1 X  t5 x# X* A+ k4 u- good understanding of ASIC mixed signal flow (Cadence based)  
4 C% s' ^: t" q5 k: M- strong background in HDL coding, verification and toplevel integration  
- good understanding of communication interfaces used in Automotive (SPI, CAN, LIN, Flexray)  
- experience in FPGA development  
- very good communication skills (written, oral)  
* f( h$ n/ F7 D' {! s) i- self motivated and high level of flexibility  
7 B' w5 K) d- m- foreign languages: English, German (not a must)

sophiew

数字IC验证工程师
) P9 X* X: Y5 Z9 u公      司：A famous IC company
工作地点：上海

0 K& Y7 J# S3 _; r8 R  v岗位职责：
1、负责整个团队验证平台的搭建、维护
2、先进验证方法和验证平台的评估、导入
3、各种IP的模块验证，SOC相关的集成验证、系统验证，负责验证计划的制定实施、测试用例的编写。

职位要求：
9 ^0 ^# d( b% T& T* V7 W* ]1、大学本科及以上学历，电子、通信、计算机或微电子专业；
2、熟练掌握Verilog、SystemVerilog、C/C++等语言的编程，有扎实的数字电路基础；
' h/ ]5 T! q* ^* P) z4 P3、熟悉SoC验证开发流程，了解常用的验证方法学，如VMM等；
3、有1~2年芯片验证的相关工作经验；
4、具有较强的学习能力、沟通能力和良好的团队合作精神；
5、有基于ARM处理器的SOC芯片验证经验者优先考虑。

ranica

ASIC Verification Engineer (WMAC)
公      司：A famous IC company
8 `  C/ f( V) t: @7 {工作地点：上海
$ O, w8 Q4 q6 S! k0 L8 }4 `
; J+ ?' I7 O0 a: x' D9 _9 O9 |The Role:
        ASIC design and verification
        Work closely with the California teams
        Support chip tape out and bring up
9 Q9 q( ^2 b; v2 c3 ^" X# O% b
Requirement:
8 k0 [7 N) |7 f1 J* a/ k" M        8-10 yrs. experience  
6 p: C. o0 {. y2 S- C, [        Knowledge of Verilog / System Verilog & Perl
% m# G6 Z0 F. I" H( i        Has worked on complex project; experience with 802.11 is preferable
8 ?2 X" }) j! e7 X/ W# l, X5 `        Can work independently - want him to take over MVE
        Experience in Networking SOC, Ethernet MAC or any other MAC layer protocol experience is plus

ranica

ASIC Digital Verification Engineer
2 d+ y# k3 N% c& [9 k公      司：A mobile chipset semiconductor company
工作地点：上海
+ n% d/ d2 D% q
Responsibilities:  
" M7 l. e4 y3 T! W( u& Q8 F- L- _! e  Make verification plan for one module or whole chip.  
  Build up and maintain module-level and chip-level verification environment  
; D6 _, S% D1 k5 [- J  Verify ASIC digital design based on case list, and output verification report.  
  Also responsible for lint checking and formal verification.  

0 X( _' _- F: K; }  s! m3 LQualifications:  
- I  {3 h. t& n, w! x5 R  _  Proficiency in logic verification.  
  Experience with Verilog logic design language.  
, m4 e3 L; f: o. u( L8 N* J  Experience with high-level verification languages such as System Verilog, System C, Vera or Specman e language.  
  Experience with UNIX/Linux simulation tools such as IUS or VCS.  
* }3 E: G* H) g' S  Experience with C and C++ is a plus.  
  Experience with C_SHELL, TCL or PERL is a plus.  
, r+ N) |3 V% {! G6 j" k  Experience with UVM, OVM or VMM is a plus.  
. l2 R- B% A" ^( }- g. ^  Good knowledge of SOC design is a plus.  
  Good knowledge of software design is a plus.  
* a+ F! ?( N+ W" S% j  Self-motivated and good team player.  
5 l6 p. z: ]- N; `: V  MSEE or BSEE with 2+ years.

ranica

Staff Verification Engineer
% N5 @3 x1 f; u" }# H: F; J1 A3 D公      司：one famous IC company
工作地点：上海

, |) q  T. b3 \. F. ^3 pQualifications
8 O5 K1 s# k2 _% u0 |& }) _MS in EE/CS/ME.  
Minimum of five  years experience.
Additional qualifications include: Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills.
Candidate should be familiar with as System Verilog, VMM/OVM/UVM verification methdology.
, c# T9 h. O4 I( y; ?Candidate should be familiar with industry standard ASIC design and verification tools and flow.
Good knowledge ddr protocol and computer system achitecture would be an added advantage.
; C" ^% Z5 W% ]. B2 T& L. qGood knowledge of Perl and shell programming would be an added advantage.  
: }( H7 z4 o& D* K2 _8 s6 R5 l
Responsibilities:
1 k' F: F& V; r' C" x3 B- O; R-Understanding the expected functionality of designs.
1 E' ]9 V4 Y: p- m' N, }" [-Developing testing and regression plans.
1 V. K9 y: ]$ O4 w: T-Designing and developing verification environment.
-Running RTL and gate-level simulations/regression.
% p5 k; c; ?8 w' H0 s  d# F2 y+ P-Code/functional coverage development, analysis and closure.
: }0 n7 y$ R6 C
1 R2 }5 u" z+ ~' URequirements:
Experience & Skill: 5 Years
-Design verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).
-Knowledge in ASIC/FPGA design process and verification tools.
-Familiar with design and verification languages (Verilog, System Verilog, SVA etc.).
' @5 L! R. G9 z- l% q7 l- Scripting and automation skills (tcl, perl, makefile etc) a plus.
4 e* s( j( W7 d7 N: p% ?1 J-Familiar with C/C++.
-Knowledge of DDR protocol a plus.
3 P; P. n6 z' x% Q" o3 {( W-Independent and self-managing.