FPGA verification Engineer most difficult job functions?

ranica

招聘公司：A fabless IC design company
招聘岗位：系统产品经理
工作地点：Beijing
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岗位描述：
主要职责： 定制芯片的实际应用方案，为客户提供具体系统应用的解决方案，统计芯片在应用中出现的问题并形成改进建议书。
$ d9 [/ E( Y4 E$ t/ H+ E
职位要求：
; Y: e8 g* e/ g5 h$ `职位需求： 1. 计算机、通信、电子工程类专业，本科及以上学历。英语CET-4级以上水平，良好的英文读写能力； 2.了解民用消费类产品的框架结构及应用领域； 3. 具备较强的芯片级理解能力，对高速视频接口（LVDS, DVI, HDMI, DP）、数字电视相关芯片有深入的研究或应用，可以很准确的知道芯片的指标含 义和解释； 4. 熟练掌握 Cadence或PowerPCB/Powerlog ic等软件，熟知原理图设计，PCB 的布线规则和产品的生产流程。能够独立调试系统板级硬件； 5. 具备敏锐和快速的反应能力；良好的思维能力、信息收集、分析能力； 6. 良好的团队合作意识和沟通能力； 7. 适应经常出差，勤奋刻苦，爱岗敬业； 8. 具有较强的嵌入式软件编程能力，熟悉LINUX系统的应用。能够独立调试系统系统软件； 9. 具有产品应用及管理经历者优先。

ranica

招聘公司：A famous IC company
招聘岗位：SoC System Verification Engineer
$ v$ ]( m7 o$ B1 V工作地点：Xi'an

岗位描述：
Job Description: * Defines and develops system validation environment and test suites. * Hardware System Validation of Baseband ICs and peripheral for Mobile Terminals Technical coordination possible depending on experience and skills * Functional verification of the baseband IC and analyze of the occurring problems * Definition and implementation of test cases for the different modules(HW/SW, Low level drivers, Linux drivers) * Lead internal customer support during the evaluation phase * Interface to Concept Engineering Team, Design Team, SW Team

ranica

职位要求：
Job Description: * BS. or MS. Degree, MS. preferred, in Electrical / Electronics Engineering or equivalent * Minimum 2 years experience with the following tools/domains are recommended: * Knowledge of Embedded system * ARM Tools (ADS), GCC know how * Script languages (GNU Make, Make, Make File structures) * Debug Tooling Multi-ICE, Lauterbach, OS-aware debugging * RTOS Symbian, Nucleus, Linux or equivalent * Usage of C models (Virtual Prototype) to test Software before silicon availability * Configuration Management (Versioning Tools: ClearCase) * Knowledge of the following cores/architecture concepts are recommended: * ARM 7/9/11/Cortex Series and all controller functions: Interrupt/DMA... * Multimedia concept: JPEG, MPEG, Camera, Display, Multimedia Card Storage devices... * Standard Interfaces (UART, SSC, I2C, USB HS, USB FS, USB HSIC, MIPI HSl, SlimBus, MIPI Unipro¿) * Memory devices (DDR1, DDR2, SDRAM, Mobile RAM, NAND and NOR Flash) * Connectivity functions: WLAN, BlueTooth, GPS, FMR... * Good English, Excellent communication skill and team spirit oriented

ranica

招聘公司：A famous IC company
招聘岗位：Digital Design Engineer
工作地点：Beijing

岗位描述：
Duties · Digital design, including synthesis, timing simulations, power optimization, DFT · Mixed signal design; and verification · Define, develop, and implement characterization, test plans, test vector generation · Work with other division test groups inside/outside FSC to identify possible co-operative opportunities to optimize test solution · Work on the design of analog blocks like voltage regulators, I/O buffer, output drivers, voltage references, oscillators · Work with product definition; characterization, and test engineers in the full product development flow; Work with application & test engineers to define optimal design and characterization solutions, based on design objectives · Layout floor planning, including P&R, DRC, LVS, and LPE
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职位要求：
7 S( h, {8 ~3 {, Z* }Requirements · Minimum 3 years direct digital IC design experience · Minimum 3-5 years direct mixed signal IC design experience · CMOS mixed signal circuit design and proficiency with industry standard design tools and Verilog/VHDL · Knowledge in CMOS/BiCMOS Analog circuit design Experience in Cadence IC Design tool set, simulation, verification · Matlab/Simulink/VerilogA or other behavioral simulation expertise a plus Team-based, cross-functional organizational structure experience preferred · Excellent written and oral communication and presentation skills · Satisfactory written and oral communication skills in English · MSEE degree or above or equivalent experience · Strong communications skills; written, verbal, presentation and listening; · Good interpersonal skills to work in a team environment; · Good command of written and spoken English required; · Excellent interpersonal, written communication and presentation skills

ranica

招聘公司：A famous IC company
" J5 L, j0 v( F: f+ B! `7 P+ i4 Q招聘岗位：Sr. Design Engineer
0 {. V: @) A- e# X6 R  g9 O工作地点：Shanghai、Beijing

岗位描述：
1 h7 Z0 l6 d) v. _5 BDuties · Analog IC circuit design, simulation and verification · Design analog products and blocks such as high current or high capacitive load output drivers, operational amplifier, comparator, voltage reference, oscillator, error amplifier, voltage regulator etc. · Design of the switching power IC, DC-DC converters, for mobile/portal application · Evaluation, simulation and analysis of power architectures and circuit topologies · IC layout including floor planning, DRC, LVS, and LPE · Work with application and testing engineers to define optimal characterization and testing solution · Work with product definers and product engineers in full product development flow
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职位要求：
Requirements · Minimum 5 years direct DC-DC IC design experience, with MSEE or above degree · Strong knowledge in analog CMOS and Bipolar IC design · Working direct experience with switching power supplies, DC-DC converters, Battery charger, and their various topologies · Theoretical understanding of the power electronics, switching power supply topologies · Prior experience with power management related IC design a strong plus · Knowledge in analog IC layout · Matlab/Simulink/VerilogA or other behavioral simulation expertise a plus · Excellent written and oral communication and presentation skills · Satisfactory written and oral communication skills in English · MSEE degree or above or equivalent experience · Strong communications skills; written, verbal, presentation and listening; · Good interpersonal skills to work in a team environment; · Good command of written and spoken English required; · Excellent interpersonal, written communication and presentation skills

ranica

招聘公司：a top 15 semiconductor company
5 E+ M- K: f0 z/ q& I& m招聘岗位：Product Engineer
工作地点：Beijing
4 [! ~" V7 Q& d7 \+ L  D4 b0 m- ]/ K  j
5 I- b( m  s/ b% A+ t0 r岗位描述：
* X( P: W, f4 U& D$ G6 U- Design database verification by simulation and on FPGA - Chip function evaluation - Develop test firmware and tools (Hardware and Software) - Develop evaluation board - Cooperate to debug chip issues - Customer support • Assist with customers’ issues • Visit customers and provide on-site support • Build up demo system

* H& m* V  d, ^* u: B  R职位要求：
, y$ |5 m) @; m) G& b; y& _- BSEE or above with minimum 3 years communication system experience - Familiar with Verilog. Has digital design experience with Verilog in real project - Minimum 3 years FPGA working experience, including code writing, timing analysis, debug - Familiar with at least one of schematic and PCB layout tools - Excellent English skill will be required. - Strong inter-personal, teamwork and communicational skills

ranica

客户 A famous IC company
% M! y5 |7 T  `6 w地点 Shanghai
0 F* t. q5 A9 |9 ^% o
" H/ T* @7 e& c职位描述
- M4 X: `( Q. q2 g& iWe are looking for a person to join a design team to execute a state-of-the-art IC design project in the wireless communication field. Candidate must be familiar with digital IC design flow with a proven record of design and verification of a complex design project that led to successful silicon. Proficiency in Verilog is required.

职位要求
5 I0 ~/ G2 |) tExperience in the following areas of expertise is desired:
Wireless media access control (MAC) design experience would be highly desirable
Knowledge of TCP/IP and DMA Offload Engine design experience will be a plus
RTL design, verification, and chip integration
Experience in the following is beneficial but not necessary requirement:
Communication systems and RF systems
0 m) ^! ^$ ~- c& ?Familiarity with wireless communication systems and standards (802.11b/g/n and WiGig)
Knowledge of interface protocols such as PCI/PCIe would be a plus
2 O* d& w) W, C1 ?( DFPGA design flow, testing, and emulation bringup

Other requirements:
/ R7 a2 _& n5 p! Z, oFamiliar with design and verification languages, EDA tools and ASIC/SOC design methodology
Good script language skill, such as Perl, Tcl and Shell
Good written and oral communication skills in English
9 F, [8 q1 c/ s! IGood Team player
9 t% W- c& `2 W0 Y- B5 s1 qCandidates must have MSEE degree with at least 5 years of experience

ranica

招聘公司：A famous IC company
8 U/ G$ I4 Y; G. ?8 L4 h7 l招聘岗位：高级ASIC设计工程师
* k8 \% d/ C: ~% ~工作地点：Shanghai
4 m+ v* b" c+ @4 P3 @
. z- k- R. U3 |; f- w) e岗位描述：
1、定义设计模块结构并编写芯片设计规范； 2、使用VHDL/Verilog编写逻辑模块的RTL代码； 3、编写测试向量对模块进行仿真验证； 4、在FPGA平台上进行芯片级的测试验证； 5、进行模块级的芯片综合与时序分析； 6、编写完整的设计和验证报告。

  x" L: |# l7 ^! a) p职位要求：
2 F- O/ e( b# T7 q1、具有电子或通信工程类硕士以上学历； 2、 熟练运用Verilog/VHDL进行芯片前端设计，熟练运用设计仿真综合和测试工具，如quartus，Xilinx，modelsim，nc，debussy，逻辑分析仪，信道仿真设备等； 3、深刻理解数字电路设计和时序分析方法，并拥有故障定位和解决问题的能力； 4、深刻理解通信原理、数字信号处理等基础知识，熟悉无线通信原理与常用算法； 5、具有3年以上芯片设计经验，拥有无线通信物理层开发项目（如DTMB、CMMB、DVB、3G, LTE等）经验者优先； 6、工作认真严谨，积极上进； 7、良好的团队合作意识和沟通能力。

ranica

Verification Engineer
1 ]( F& T; d8 U: V
公      司：A famous IC company
工作地点：上海
+ D+ `7 K# }1 v' k' k3 K
The Role:
·         ASIC  verification
4 p& q' i( ^8 a& v( m; m, q·         Work closely with the California teams
5 ^6 I6 _! n  _1 l8 R·         Support chip tape out and bring up

% k+ j" f9 ]* S3 O! |& F3 }Requirements:
·         3+ years experience in ASIC Verification
·         BS in Electrical Engineering (or equivalent) is a must have, MSEE is desired
, w/ I& h1 t3 j& u/ G0 F, Q1 {8 @( J·         System on Chip (SOC) Verification Experience, including AHB/AXI, CPU, Interface integration verification
·         Very familiar with verification languages – Verilog, System-Verilog, and VMM
·         Test plan and test case documentation
& J7 L/ f0 p' A( D" b·         Functional coverage and code coverage analysis
/ a/ @6 ^6 l5 C" N+ m% D·         Must be familiar with various scripting languages used in verification, including Perl, Csh, Make, etc.
·         Experience verifying interfaces such as PCIe, Ethernet, DDR, USB
# L" x0 r' Y5 d) y: M- I9 [·         Working knowledge of networking protocols 802.3 and 802.11, especially Medium Access Control and TCP/IP
·         Working knowledge of C programming language
" B+ s# Y: e- u0 [" _" D7 M3 [·         Must be familiar with the ASIC verification flow from feature identification to test bench development and through final tape out sign-off
& @7 i: B! ], a* L) k5 ^+ P·         FPGA emulation experience a plus
·         Chip bring-up experience, including use of Logic Analyzer and Oscilloscope for debugging

ranica

ASIC Digital Verification Engineer
公      司：A mobile chipset semiconductor company
工作地点：上海
( `0 r" q4 d  J) ?; O/ ^. |3 w$ D. [4 F
Responsibilities:  
* N& u7 |4 b& I; k1 w( s! _  Make verification plan for one module or whole chip.  
  Build up and maintain module-level and chip-level verification environment  
  Verify ASIC digital design based on case list, and output verification report.  
  Also responsible for lint checking and formal verification.  
% O4 K% O! W$ U" _, d
Qualifications:  
1 l$ B" L: }8 B2 G+ s! }& Z  Proficiency in logic verification.  
; {: O0 T6 `7 n, D  Experience with Verilog logic design language.  
  Experience with high-level verification languages such as System Verilog, System C, Vera or Specman e language.  
$ R6 [  y8 Y% S$ \) r  Experience with UNIX/Linux simulation tools such as IUS or VCS.  
* E5 A2 N9 s3 o5 W% }, y2 o, g% P  Experience with C and C++ is a plus.  
  Experience with C_SHELL, TCL or PERL is a plus.  
  Experience with UVM, OVM or VMM is a plus.  
  Good knowledge of SOC design is a plus.  
  Good knowledge of software design is a plus.  
  Self-motivated and good team player.  
  MSEE or BSEE with 2+ years.

tk02561

Hardware Applications Engineer–Graphics
, m# }3 A* v" _: c7 z  _/ y公      司：A famous IC company
工作地点：上海
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Desirable
Strong understanding of microprocessors
A good understanding of the interaction between software and hardware
Understanding of FPGA or ASIC implementation flows (synthesis, scan insertion, layout)
% T: ^6 v4 B8 F. EC/C++, assembler coding or other programming skills.
Knowledge of GPU or graphics processing specification, like OpenGLES, Direct-X, is preferred

, |2 w& P' T; A$ X- LJob Requirements：

tk02561

Education
4 U/ s% o& Y0 \0 ]" V7 fGood university degree, in Computer Science or Electronics Engineering ideally, although other science graduates would be considered if they have relevant experience.
  
; w# M# x! O$ gExperience
Minimum of 4 years industrial experience
4 W- o; z$ A: ?  n1 C. V. vExperience or knowledge of FPGA or ASIC design, simulation and/or verification techniques, including RTL coding and simulation, in Verilog or VHDL
1 `: C+ h' x' C+ yExperience in integrating SoC peripherals
Experience of interacting with colleagues outside of China
Professional experience of customer and sales interaction
* h+ e( d3 T( dDemonstrable experience of problem solving and debug skills

Personal Requirements
6 R  N' H" t( b. a1 n/ \/ L' |Must have excellent written and verbal communication skills with both colleagues and customers, including good written and spoken English
' k, s5 S7 F! MMust be proactive in obtaining engineering or management input, in order to complete project and internal tasks in a timely and accurate manner
  ?8 y. @, t8 G% y, t2 oMust have the desire and ability to solve problems quickly
" X# i( E1 N' q/ m" Y: k* ]. RMust be enthusiastic and well driven
Must be able to schedule own workload and plan tasks – based on both internal and customer requirements.  
Must have good inter-personal skills, and be able to work well within a team; especially when under pressure
Must be willing to be flexible and accept new challenges
Must be able to travel on a regular basis, both to give customer training and also for internal business reasons.

ranica

Senior Digital Design Engineer
# X$ k1 E$ ^3 Z0 k  R% {+ T公      司：A leading semiconductor company
工作地点：香港

/ J3 D, R) ^. [9 s7 g; RJob Responsibilities:
3 m: M. Q( {: t  r& p    Perform logic design, RTL coding, design verification, logic synthesis, DFT and static timing analysis
' k: i7 r* \- o; p- ~: N$ W& Z. L    Develop verification environment and coverage closure
    Support wafer level testing and silicon evaluation
    Prepare technical documents
+ M3 X& E$ m- }# ]
Job Requirements:
$ `- H- x, b9 n9 k( `    B.Sc or above in Electronic Engineering or equivalent. Applicants with postgraduate degree would be considered as an advantage
) E. k+ c6 M+ l    5 Years or above of solid experience in one or more of the following areas: Verilog-based logic design and synthesis, constrained random    testbench with System Verilog & UVM, assertion based design verification or circuit-level SPICE simulations
    Knowledge of SoC and embedded system.
4 d* G% A2 ]# \0 X    Knowledge of scripting languages such as Perl, TCL and Make
* r2 Q$ X/ J0 \) Z! |6 _) T2 }    Candidate with less experience will be considered as Digital Design Engineer

ranica

数字IC验证工程师
公      司：A famous IC company
工作地点：上海
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1 @- \# c  `7 }3 J岗位职责：
1、负责整个团队验证平台的搭建、维护
& ^5 y1 [1 N% I) f6 }3 K$ b2、先进验证方法和验证平台的评估、导入
3、各种IP的模块验证，SOC相关的集成验证、系统验证，负责验证计划的制定实施、测试用例的编写。
% W# k. x; ]& l; a+ u" [
职位要求：
$ X4 j2 s$ V8 r$ w4 t1、大学本科及以上学历，电子、通信、计算机或微电子专业；
; ]; W. d# o* x; W7 L* O# U2、熟练掌握Verilog、SystemVerilog、C/C++等语言的编程，有扎实的数字电路基础；
3、熟悉SoC验证开发流程，了解常用的验证方法学，如VMM等；
3、有1~2年芯片验证的相关工作经验；
( `" B& i0 l* Y) @$ E$ y! U4、具有较强的学习能力、沟通能力和良好的团队合作精神；
5、有基于ARM处理器的SOC芯片验证经验者优先考虑。

jcase

数字IC验证工程师
公      司：A famous IC company
工作地点：上海
/ B3 P0 g8 g/ X5 M* @# \
岗位职责：
; p3 g3 ?5 p" w4 H/ s  q( G1、负责整个团队验证平台的搭建、维护
6 f2 I" J- ]& t# \2、先进验证方法和验证平台的评估、导入
! }  ?2 _4 x2 W" }( b2 @! c3、各种IP的模块验证，SOC相关的集成验证、系统验证，负责验证计划的制定实施、测试用例的编写。

职位要求：
9 ]0 x) n3 V2 S/ [1、大学本科及以上学历，电子、通信、计算机或微电子专业；
2、熟练掌握Verilog、SystemVerilog、C/C++等语言的编程，有扎实的数字电路基础；
2 l. g3 [8 z7 g% I7 i  `% h) d9 M3、熟悉SoC验证开发流程，了解常用的验证方法学，如VMM等；
# F! o3 `; l" h! U/ u& a) o3、有1~2年芯片验证的相关工作经验；
. W# S5 }0 d7 q! C" j/ n" r4、具有较强的学习能力、沟通能力和良好的团队合作精神；
5、有基于ARM处理器的SOC芯片验证经验者优先考虑。

ranica

Senior Digital Design Engineer
; G4 ?+ ~  f; `7 q& f4 q* J( _公      司：A famous European IC company
工作地点：上海

Job description  
- define system partitioning of s/c circuits and system  
* O. N! n! }! N0 D6 p. U9 E! s# @- define HW/SW co-partitioning  
, M0 L& [2 o4 V6 N0 ^- provide technical feasibilities based on system simulation and/or FPGA based demonstrator  
6 c9 y+ X6 }# U% L& E! G! i% C- propose new technical solutions on s/c and system level  
* ~" R3 f% f3 U/ ?1 T- design digital part of mixed signal (smart power) ASICs  
! F+ c: ?; s+ k' b; ^7 O0 r- close cooperation and interaction with international teams  
" K$ e5 T) G, |4 \9 G- coach junior engineers  
3 L( @2 _! n' R1 e3 d% P
( O2 Y8 R' z# v7 \$ }! \% aRequired knowledge competencies and attributes  
+ ~+ n& m2 }* _) p' l1 C" p- master degree in microelectronic circuits or systems, Communications, Computer Engineering (or equivalent)
/ \- c) L, L- w# U- > 5ys experience in digital design  
- good understanding of ASIC mixed signal flow (Cadence based)  
! J( h8 L8 M1 a2 ^. Q8 M- strong background in HDL coding, verification and toplevel integration  
' f  ~; d7 ~; P$ j- good understanding of communication interfaces used in Automotive (SPI, CAN, LIN, Flexray)  
- experience in FPGA development  
- very good communication skills (written, oral)  
7 O1 U/ f! l8 A( {- self motivated and high level of flexibility  
- foreign languages: English, German (not a must)

sophiew

数字IC验证工程师
, S' H3 w6 @; e7 e公      司：A famous IC company
工作地点：上海

: W0 {4 X% y1 c: Z+ I" b岗位职责：
' ^0 O* Z; W0 r7 q6 X1、负责整个团队验证平台的搭建、维护
2、先进验证方法和验证平台的评估、导入
$ S0 ^% p3 B$ |- |& n; p3、各种IP的模块验证，SOC相关的集成验证、系统验证，负责验证计划的制定实施、测试用例的编写。
; f* Y3 K+ X3 u' }8 A
职位要求：
2 s/ J' F8 i8 M/ x( Q7 |1、大学本科及以上学历，电子、通信、计算机或微电子专业；
2、熟练掌握Verilog、SystemVerilog、C/C++等语言的编程，有扎实的数字电路基础；
* T3 r0 S8 X' I( E3 a. [5 c3、熟悉SoC验证开发流程，了解常用的验证方法学，如VMM等；
3 a% J+ |8 V6 }6 E2 g3、有1~2年芯片验证的相关工作经验；
( a2 Y7 u2 o0 j4、具有较强的学习能力、沟通能力和良好的团队合作精神；
! s3 m* b! u# d' ~- c; ~$ n4 Z% K5、有基于ARM处理器的SOC芯片验证经验者优先考虑。

ranica

ASIC Verification Engineer (WMAC)
1 r/ s2 P- K) R( B公      司：A famous IC company
' V6 g* Q# B9 s$ r工作地点：上海

# w$ a# V) X9 d% Z! T; _7 MThe Role:
        ASIC design and verification
        Work closely with the California teams
: d/ X$ g$ ^) [: ~. c) |        Support chip tape out and bring up

; n+ v% u$ X2 a* d8 |8 fRequirement:
" G8 l; F$ m. [2 D+ l        8-10 yrs. experience  
" C' V& O/ ?5 `' V/ G) B! G$ U        Knowledge of Verilog / System Verilog & Perl
        Has worked on complex project; experience with 802.11 is preferable
; p8 c% ?* o6 D8 P$ ^/ q9 T        Can work independently - want him to take over MVE
$ h5 R. r. K  n) i) _# c( V        Experience in Networking SOC, Ethernet MAC or any other MAC layer protocol experience is plus

ranica

ASIC Digital Verification Engineer
5 Y- c7 ]' i" a/ U. K! ~公      司：A mobile chipset semiconductor company
8 k9 R/ Z5 p2 I/ t# M+ t工作地点：上海

1 J& {2 H4 M4 J2 HResponsibilities:  
/ N* n, o! a& V5 V  _  Make verification plan for one module or whole chip.  
  Build up and maintain module-level and chip-level verification environment  
  Verify ASIC digital design based on case list, and output verification report.  
1 N! D; n) q/ J; Q2 L3 b  Also responsible for lint checking and formal verification.  
  a, V1 w" f/ S& |) b$ a$ |
Qualifications:  
  Proficiency in logic verification.  
" {7 W$ ]. I' q7 n/ A( V8 ~  Experience with Verilog logic design language.  
( S4 |' e. }6 W, [5 f: i3 M  Experience with high-level verification languages such as System Verilog, System C, Vera or Specman e language.  
# }+ e- R9 K* |3 O6 `  Experience with UNIX/Linux simulation tools such as IUS or VCS.  
  Experience with C and C++ is a plus.  
" t0 x& F3 w1 E. `5 Z. d, D  Experience with C_SHELL, TCL or PERL is a plus.  
  Experience with UVM, OVM or VMM is a plus.  
, l+ [. s! o  @+ T4 j2 ?! X! _7 E  Good knowledge of SOC design is a plus.  
5 j  |9 W2 v' ~$ K1 K  Good knowledge of software design is a plus.  
  Self-motivated and good team player.  
  MSEE or BSEE with 2+ years.

ranica

Staff Verification Engineer
2 B0 @, |5 K# s" v# w7 s, W4 c公      司：one famous IC company
工作地点：上海

Qualifications
- E) t4 P, R9 H$ jMS in EE/CS/ME.  
+ j  N8 Q* a# s4 {5 ]Minimum of five  years experience.
Additional qualifications include: Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills.
8 z0 @8 o$ b! f' jCandidate should be familiar with as System Verilog, VMM/OVM/UVM verification methdology.
9 y7 K3 _; [- C& J, I% [Candidate should be familiar with industry standard ASIC design and verification tools and flow.
4 @+ j/ g) }! sGood knowledge ddr protocol and computer system achitecture would be an added advantage.
" [0 b, S, v4 N7 H. x( WGood knowledge of Perl and shell programming would be an added advantage.  

6 I, |1 B; U$ ^( X  k1 [5 J/ jResponsibilities:
3 c2 o* l- f! z0 l+ U-Understanding the expected functionality of designs.
-Developing testing and regression plans.
2 \5 l+ X+ w3 i( `" A# S6 Y# ?-Designing and developing verification environment.
-Running RTL and gate-level simulations/regression.
4 m7 ?  a5 E8 l. v# ?9 b/ p# V+ \; r4 T-Code/functional coverage development, analysis and closure.
& C, A2 U5 Z! H
& k$ z+ ]- o5 {7 t4 D( k) URequirements:
Experience & Skill: 5 Years
+ f+ K3 V% D$ t+ d" T6 \-Design verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).
5 G1 N8 W) M5 P. x  d* ?-Knowledge in ASIC/FPGA design process and verification tools.
-Familiar with design and verification languages (Verilog, System Verilog, SVA etc.).
- Scripting and automation skills (tcl, perl, makefile etc) a plus.
-Familiar with C/C++.
8 H; S8 q2 _7 N6 D  Z6 p-Knowledge of DDR protocol a plus.
-Independent and self-managing.