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Configuration Management Engineer (Digital IC Design)請進來交流!

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發表於 2011-7-20 12:12:57 | 只看該作者 回帖獎勵 |倒序瀏覽 |閱讀模式
招聘公司:A famous IC company
* i) p$ s7 z. Z$ V) Y0 s( C2 U7 ^招聘岗位:(Senior) Configuration Management Engineer (Digital IC Design)% d. U) C" Y6 ^  H, @
工作地点:Shanghai
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9 t5 R+ h; Y0 C0 i9 t7 w岗位描述:
) {2 v$ f3 a3 |& y" Y! Y9 @! C; h8 GDuties · Do database management/configuration management to support Digital SOC product development for mobile phones · Administrate Clearcase /DesignSync · Administrate change control and bug tracking tools · Do linux/LSF compute farm/ CAD tool first-level support to Digital SOC design team and interface to company IT/CAD organization · Take charge of CAD investment request consolidation
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- `$ O1 ?/ V  h( c: X5 m职位要求:4 B- F( D( P- e( T& x: D
Requirements · B.Sc. degree or above in Semiconductor, Electronics Engineering areas · 2 years or above experience in Clearcase/DesignSync administration and configuration management in Digital IC Design domain · Good knowledge of digital SOC design is a big plus · Good knowledge of linux, LSF compute farm and script writing (e.g. C shell, Perl) · Good communication skill, will have frequent communication with foreign teams. · Good written and spoken English is mandatory.
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+ m! x+ }0 k# H$ e能者與意者請email研發簡歷與chip123聯絡。
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 樓主| 發表於 2011-7-20 12:15:58 | 只看該作者
招聘公司:A famous IC company1 }- F8 x; T% \# H5 C
招聘岗位:(Senior) Digital IC Design Engineer (FE Design)
* t$ ]8 E; w% x1 d* k( W工作地点:Shanghai
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5 C9 ]% f# ?6 K( n% ~, G岗位描述:5 A# w5 C0 G( R/ X- G$ `( N' F. I
Duties • IP design and support for digital baseband of cellular phones • Digital SOC design and integration for chips
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9 |7 S* N& @2 `% [职位要求:- p+ h8 J, P( ?& g$ ]/ Z
Requirements • B.Sc. degree or above in Semiconductor, Electronics Engineering areas • 2 years or above design experience in industry • Good knowledge of design flow including documentation, VHDL/verilog coding, code check, equivalence check, synthesis, timing analysis and RTL simulation. • Good knowledge of AMBA AHB/AXI protocol is preferred. • Good knowledge in UPF/IP-XACT based design flow is a big plus. • Hands on experience in digital IC design EDA tools, such as NCSim/Questasim, Design Compiler, Formality, Primetime etc. • Good communication skill, will have frequent communication with foreign teams. • Good written and spoken English is mandatory.
3#
發表於 2012-4-16 11:36:53 | 只看該作者

Staff Engineer for Digital MAC Design

客户 A famous IC company0 {* E& Q. ^! I" }+ u& \
地点 Shangha) ^9 P* [  |+ X( h! T0 Z# y. W
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职位描述; a' n) n6 L0 o4 a4 x: \+ S
We are looking for a person to join a design team to execute a state-of-the-art IC design project in the wireless communication field. Candidate must be familiar with digital IC design flow with a proven record of design and verification of a complex design project that led to successful silicon. Proficiency in Verilog is required., ]( f& J$ z8 v7 E* }" J
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职位要求
# F5 f3 X( [9 P& n, mRequirements:
8 x3 F; t$ d+ j* H) L9 y1 SExperience in the following areas of expertise is desired:; W2 I7 H) v% b& L1 n9 S: y; m; O
Wireless media access control (MAC) design experience would be highly desirable
6 D  `6 \, S$ v' }% XKnowledge of TCP/IP and DMA Offload Engine design experience will be a plus
; Q6 ]4 N) [- I4 C' [/ k3 u, WRTL design, verification, and chip integration
4 |; \5 I, n6 c- h/ c0 TExperience in the following is beneficial but not necessary requirement:; U) l1 |0 o" c% y. T  X3 M
Communication systems and RF systems* r4 K' Z: b8 e
Familiarity with wireless communication systems and standards (802.11b/g/n and WiGig)' `6 M( Y! o% L( O
Knowledge of interface protocols such as PCI/PCIe would be a plus
2 V' Z! N" g' Z+ tFPGA design flow, testing, and emulation bringup
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' T) y$ r4 a/ J1 x  F, UOther requirements:
# L- \. V% c6 N- A' mFamiliar with design and verification languages, EDA tools and ASIC/SOC design methodology5 @! G. s# c2 W' h4 u+ s" [0 s9 g
Good script language skill, such as Perl, Tcl and Shell;
4 ]# Y1 \8 S: {Good written and oral communication skills in English;
& W* D2 o: j8 HGood Team player
" _2 E9 i$ ^: Q+ Z7 p7 g+ t& ACandidates must have MSEE degree with at least 5 years of experience
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