請教 Synplify "reduced to a combinational gate by constant propagation"

kuhwakimo

請教 Synplify Pro9.6.1 Warning Message
Sequential instance sLateCol_p has been Sequential instance sLateCol_p has been reduced to a combinational gate by constant propagation

% V" Q5 ^) E; P0 k' {請教個問題，下面是Synplify 9.6.1 出現的Warning message ,
) M  k6 F" d# |請問這是什麼意思　??
我由字面上的理解得到的猜測是，將一個本應該是FIFO Sequential circuit ,合成為 Multiplier Combinational circuit
為什麼　ld_tdr_cur_f　會被合成為Combinational, 但是 dly_tdr_wrn 卻不會 ??
6 Q) |* ]% J+ E# q0 S6 ]& i* J誰有相關的經驗嗎 ??

/ `( H( \# |) k1 ^; }6 T- X@W: MO129 :"\projects\dm8606c\rtl\tff256x64.v":932:3:932:8|
& O% s6 R- ^0 j( O; i, nSequential instance ld_tdr_cur_f has been reduced to a combinational gate by constant propagation
  F: O% D  o3 O1 [5 j. Y6 A2 ?
7 `/ u0 y. C) L2 E5 C
7 f- X5 j6 T+ S" w2 W3 o     reg ld_tdr_cur_f;  
& B4 a; i9 d3 g7 F! m     reg dly_tdr_wrn;
   //------------------------
   // delay 1 clk
, a5 W3 }4 H5 V" L5 r   //------------------------
  C/ n& X% ~5 r" f   always@(posedge sclk)
   begin
      ld_tdr_cur_f <=#td1 ld_tdr_cur;
      dly_tdr_wrn  <=#td1 tdr_wrn;
   end
+ [+ F0 {. H$ s% j5 K7 C
// 下面是 ld_tdr_cur_f , dly_tdr_wrn 的loading

* k9 k% H: R+ a- q7 l0 A! X3 R2 N' i   always @(posedge sclk)
% [! U$ n0 I/ z      if (ld_madr & !wr_nxt_tdr)  
         wr_save_1st <= #td1 wr_counter;
( [0 P! Y* e& }3 P      else if (ld_tdr_cur_f)      
3 Z6 E! X0 J4 b1 z         wr_save_1st <= #td1 wr_save_2nd;


   always @(posedge sclk or negedge rstn)
      if (!rstn)      
. r. ^7 G$ w; s! C         rst_ff_pt <= #td1 1'b0;
% k: l6 p0 J3 a6 V8 I# n      else
         rst_ff_pt <= #td1 (!tdr_wrn & dly_tdr_wrn & tdr_empty);
- T8 x3 ^7 m+ z5 [0 t         


7 G+ _- X4 N+ ]  c& v$ A5 Q   always @(posedge sclk or negedge rstn)
6 L, [& e0 l) {1 T3 y      if (!rstn)      
7 x- E3 _3 Z7 Q* ?- E' t4 p5 R         rst_ffpt_sync <= #td1 1'b0;
      else if (!tdr_wrn & dly_tdr_wrn & tdr_empty)
. o9 f7 @) N. F. J/ H+ t  J         rst_ffpt_sync <= #td1 1'b1;
( c) H2 c) I0 p3 J6 S9 {      else if (rst_ffpt_clr2)  
  E( E8 L. [  e; W# O3 x* b         rst_ffpt_sync <= #td1 1'b0;

yadog

不清楚要实现什么功能

4 ]" I( e+ Y# E$ p# g% p但是在写法上有些问题
6 O" `: R. V  N. N2 n" S
% N7 B* \1 C, d  o# S- @if (ld_madr !wr_nxt_tdr)   这句是否笔误？ld_madr ，wr_nxt_tdr是两个信号把？

  x; i$ f9 F1 ^! G另外if else if写法均不完备，建议将else项完备

kuhwakimo

是貼上去的時候出現亂碼,更正如下   
( P5 u% X2 D3 U- K7 T5 C. c# T//------------------------
$ L5 q' X, l# r+ r  H4 D+ p) w   // save start pointer for 1st pkt
   //------------------------
   always @(posedge sclk)
8 J+ F$ p0 M! e$ q, K. S8 i      if (ld_madr & !wr_nxt_tdr)  
: M# n! \" {- \9 O% R         wr_save_1st <= #td1 wr_counter;
0 ?' n+ T: P% R$ g# `9 f      else if (ld_tdr_cur_f)      
         wr_save_1st <= #td1 wr_save_2nd;