超越摩爾定律 賽靈思領先全球推出堆疊式矽晶互連技術

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全新技術大大擴展FPGA版圖，為FPGA帶來全新密度、頻寬、及省電效率
# y# a7 _# h8 ~1 R& \相較於單片型元件，可提高100倍每瓦的晶粒間頻寬，且增加2至3倍容量
照片1:賽靈思全球資深副總裁湯立人(右)與台積電研發資深副總經理蔣尚義博士(左)持晶片合照


" |. E3 h0 t3 t7 \" w6 p: N全球可編程平台領導廠商美商賽靈思（Xilinx, Inc.(NASDAQ：XLNX)）今日宣佈發表業界首創的堆疊式矽晶互連技術，帶來突破性的容量、頻寬、以及省電性，將多個FPGA晶粒整合到一個封裝，以滿足各種需要大量電晶體與高邏輯密度的應用需求，並帶來可觀的運算與頻寬效能。透過採用3D封裝技術和矽穿孔(TSV)技術，賽靈思28奈米7系列FPGA特定設計平台(Targeted Design Platform)能夠滿足系統在各方面的資源需求，提供比其他最大型單晶粒FPGA高出超過兩倍的資源。此款創新平台模式不僅讓賽靈思超越摩爾定律的限制，並為電子產品製造商系統的大規模整合提供無與倫比的最佳化功耗、頻寬、以及密度。  
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. G7 G  V* k% o. Z+ _9 A賽靈思公司資深副總裁Vincent Tong表示：「賽靈思的28奈米7系列FPGA透過提供領先業界，數量最高達200萬個邏輯單元的最大容量，大幅擴展可編程邏輯的應用範圍。我們的堆疊式矽晶互連封裝技術，將完全實現這項卓越成就。賽靈思經過5年的精心研發，加上台積電領先業界的技術，使我們能推出創新的解決方案，協助電子系統研發業者在其製造流程中發揮FPGA的各種強大優勢。」

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照片2:賽靈思亞太區行銷及應用總監張宇清(最右)賽靈思全球資深副總裁湯立人(右)台積電研發資深副總經理蔣尚義博士(左)賽靈思台灣區銷售總經理王漢傑先生(最左)合照

賽靈思目前已為客戶推出ISE Design Suite 13.1試用版，透過其中的軟體支援，28奈米Virtex-7 LX2000T元件將成為全球首款多晶粒FPGA，其邏輯容量比賽靈思目前40奈米世代中具備串列收發器的最大型FPGA要多3.5倍，而且比最大競爭類別的內建串列收發器的28奈米FPGA要多2.8倍。此元件採用領先業界的微凸塊組裝技術，加上賽靈思具備專利的FPGA創新架構，及台積電先進的技術，與採用多個FPGA之技術相比，能提供更低功耗、系統成本、以及電路板複雜度，可在相同封裝內支援相同應用。
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台積電研發資深副總經理蔣尚義博士表示：「與傳統單片型FPGA相比，多晶片封裝的方式，是一項創新作法，可提供大規模可編程功能，理想的良率、可靠度、溫度梯度、以及抗壓力等特性。透過採用矽穿孔技術及矽插技術(silicon interposer)，來實施堆疊式矽晶互連方法，以這些良好的設計測試流程為基礎，賽靈思預計將可大大降低風險，並順利走向量產。 透過此流程，公司將能滿足在設計執行、製造驗證、以及可靠性評估等業界標準。」

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照片3:賽靈思亞太區行銷及應用總監張宇清(最右)賽靈思全球資深副總裁湯立人(右)台積電研發資深副總經理蔣尚義博士(左)賽靈思台灣區銷售總經理王漢傑先生(最左)持晶片合照

8 l' X8 j8 U; m+ U$ ~' S在賽靈思的堆疊式矽晶互連結構中，相鄰FPGA晶粒之間的資料傳輸會經過超過1萬個路由管線。相較於採用標準I/O連結來整合一個電路板上的兩個FPGA，堆疊式矽晶互連技術可提供超過100倍的每瓦晶粒間連結頻寬，且傳輸延遲只有五分之一，而且不會耗用任何高速序列或平行I/O資源。透過讓晶粒彼此緊鄰，並連結至球狀閘陣列，賽靈思藉此避免以往採用單純垂直晶粒堆疊法，會產生的熱流與各種設計工具流程的問題。賽靈思基礎FPGA元件採用28奈米HPL(高效能、低功耗)製程技術，為封裝內FPGA晶粒的整合提供充裕的功耗預算。

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9 A$ Z0 K7 E9 j8 P  R. c賽靈思堆疊式矽晶互連技術示意圖
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1 d6 G0 g3 g- x( _( R賽靈思的堆疊式矽元件互連技術能支援各種要求最嚴苛的FPGA應用，這些元件正是許多新一代電子系統的運算核心。這項技術的超高頻寬、低延遲、以及低功耗互連等優異特性，讓顧客能運用和大型單片FPGA元件一樣的方法建置各種應用，並利用軟體內建的自動分區功能，提供按鈕式的簡易運用方式，並能運用階層式與團隊分工的設計方式，達到最高效能與生產力。  
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+ X& d$ }4 b' t$ k, k) FARM公司系統設計部執行副總裁兼總經理 John Cornish 表示：「Virtex-7 2000T採用堆疊式矽晶片內連線技術，是FPGA發展史上的一個重要里程碑，它將讓ARM能把最新的核心與平台解決方案建置在單一FPGA內。相較於多個FPGA的設計方案，這將能大幅減輕我們的研發工作負荷、降低元件功耗。我們的ARM Versatile Express SoC原型設計解決方案長久以來一直採用Virtex FPGA技術，此新技術將更進一步鞏固我們的領先地位。」
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賽靈思透過採用經驗證的 TSV 技術，以及目前正被廣泛高效率使用的低延遲插入式結構，將進一步豐富其 FPGA 產品的功能。賽靈思所使用的技術也一直被高量產的製造環境所採用，因此預計成品將具有穩定的高品質及高可靠性，且客戶風險會非常低。

5 ~4 m4 V( q6 U3 S9 K( g6 ~$ d除了矽元件的發展外，賽靈思也與業界領先的一線晶圓製造，以及代工組裝與測試廠合作，包括像台積電這樣的先進大廠，以建立強大可靠的供應鏈。目前已向客戶推出的ISE Design Suite 13.1試用版將提供軟體支援。首批元件預計將於2011下半年開始供貨。

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Xilinx Stacked Silicon Interconnect Technology Announcement
0 b: B2 x$ @  I8 FEmbargoed News: Oct. 27, 2010
; l% A* E5 O, t1 F5 Z: }) o' J) e8 VXilinx Stacked Silicon Interconnect Extends FPGA Technology to Deliver “More than Moore” Density, Bandwidth and Power Efficiency
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! M0 Q$ _& b$ s% i4 u! ^6 ?7 z1.What is Xilinx announcing?
Xilinx is taking a 3D packaging approach it calls Stacked Silicon Interconnect technology that uses passive silicon-based interposers, microbumps and through-silicon vias (TSV) to deliver multi-die programmable platforms. For applications that require high-transistor and logic density for high levels of computational and bandwidth performance, these 28nm platforms will deliver significantly higher capacities, resources and power savings than possible in a monolithic die approach.  

2.What does Xilinx mean by “More than Moore”?
9 K  o4 G4 ]% g  tTo date, with every process node, FPGAs have followed Moore’s Law, doubling logic capacity while costing half as much. Unfortunately, merely relying on Moore’s Law increases no longer addresses the insatiable market demands for greater resources at manageable levels of power consumption and foundry yields. Stacked Silicon Interconnect technology enables Xilinx to provide a viable programmable solution that overcomes these challenges.
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3.Why can’t customers simply interconnect two or more FPGAs to implement large designs?
: T* s  o# a3 UThe shortcomings of this approach are threefold: the limited number of I/O available is insufficient for connecting the complex networks of signals that must pass between FPGAs in a partitioned design as well as for connecting the FPGAs to the rest of the system; the latency of signals passing between FPGAs limits performance; and using standard device I/O to create logical connections between multiple FPGAs imposes an unnecessary power consumption penalty.

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4.Are there any special thermal management concerns when using Stacked Silicon Interconnect technology?
% }* B( f. Z+ x: Y3 zNo. Because the interposer is passive, it does not dissipate any heat beyond what is consumed by the FPGA die.  Stacked Silicon Interconnect technology FPGA devices are, therefore, comparable to a single die if such a large monolithic device could be manufactured.

5.Is Stacked Silicon Interconnect technology reliable?
: q5 W$ f5 _8 t; [+ qYes, in general, internal stress of Stacked Silicon Interconnect technology package architecture is lower than the equivalent size of monolithic flip-chip BGA package since the thin silicon interposer effectively decouples any internal stress build up. Therefore, thermo-mechanical performance improves by reducing maximum plastic strain in the package.
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6.Who is expected to use the FPGAs made with the Stacked Silicon Interconnect technology?
. |1 ^4 C, d5 h- f3 e) x4 d7 M1 @' HCustomers in Communications, Medical, Test and Measurement, Aerospace and Defense, High Performance Computing, and ASIC prototyping (emulation) who are looking to implement their next-generation, most demanding applications with FPGAs are likely to benefit from the earlier availability of the most resource-rich FPGA devices.   By not having to drive off-chip through I/Os (parallel or serial), across PCB traces to adjacent FPGAs, designers that have previously used multiple FPGAs in their system will appreciate the high-bandwidth, low-latency, power-efficient interconnect between the FPGA die.

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7.What design guidelines will Xilinx provide for devices using Stacked Silicon Interconnect technology?
Xilinx’s ISE® Design Suite will provide new and updated features to help with designing for the Stacked Silicon Interconnect technology FPGA devices.  There are several design rules checks (DRCs) and software messages to guide users on logic placement and routing between FPGA die.  Additionally, the graphical representations of the FPGAs with Sacked Silicon Interconnect technology is enhanced in PlanAhead and FPGA Editor to assist with interactive design floorplanning, analysis and debug.  Additionally, an application note providing users with detailed guidelines on best design practices is in development and will be available.
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; K, J* S+ k  u, j3 M8.Do customers have to partition designs or will the software do that for them?
The software will automatically distribute designs into the FPGA die without any user intervention.  If desired, users may floorplan logic to reside within specific FPGA die.  In the absence of any such constraints the software tools have the algorithms to intelligently place associated logic within the FPGA die respecting inter- and intra-die connectivity and timing.

9.What product will use Stacked Silicon Interconnect technology?
2 b! K4 U4 w. M4 UThe Virtex®-7 2000T device, the largest member of the Virtex-7 family offering two million logic cell capacity and thirty-six 10.3Gbps transceivers, will be the first realization of the technology. Initial shipments are scheduled for the second half of calendar year 2011.

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1.What is Xilinx’s 7 Series?
The new 28nm Artix™-7, Kintex™-7, and Virtex-7 families announced in June 2010 extend Xilinx’s Targeted Design Platform strategy by combining breakthrough innovations in power efficiency, performance/capacity, and price/performance with unprecedented levels of scalability and productivity to make programmable logic more accessible to a broader community of users, end markets and applications. The 7 series FPGA families all share a unified architecture implemented on 28nm process technology optimized for low power with high performance. This unique combination delivers 50% total power reduction and enables a 2X price/performance improvement, 2X increase in system performance and the world’s first 2 million-logic-cell FPGA (providing 2.5X higher capacity compared to previous generations). As a result, designers can easily scale their applications for system performance, capacity, or cost within and across the 28nm families while staying within power budgets.

2.When will Xilinx 7 series FPGAs be available in software?
+ a! C: ]; S4 b/ kEarly access ISE® Design Suite software supporting the new FPGA families has been shipped to early adopter customers and partners.
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7 c3 p( Z/ y, `4 J5 J/ O3.When will the new 28nm devices begin shipping?
First shipments will begin in the first quarter of calendar year 2011.
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wp380_賽靈思堆疊式矽晶互連技術公司白皮書.pdf
IBS 白皮書_賽靈思堆疊式矽晶互連技術_Oct 2010_.pdf
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