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//可直接透過synthesis tool用於PLD，FPGA不可 LUT delay則要採其他方式。
. Y) c' f( L+ v//所有註解都要保留8 _' j. r/ R7 H' M: D
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`timescale 1 ns / 1 ns |/ o# U* K6 E0 i2 g' ^2 L
module xclk(sclk,ena,set,outp);
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input sclk,ena;& B+ y) I1 u$ Y# K9 S& @* o& P
input [1:0]set;
5 F t( e) A) G$ {, S! Aoutput outp;
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3 B/ i F9 Q4 o9 twire outp;
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$ P% B+ a: L0 Y# t/**** Node preservation for nodeA **************/
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//exemplar attribute nodeA_5 preserve_signal true3 u/ a- s, D+ |5 @: Y( S5 W# ^
+ t" r) S5 b9 J5 J+ P# p4 M! b, I//exemplar attribute nodeA_4 opt keep1 Q1 }; V* A( v9 Y" o* `5 e
6 d* H: p- U Q9 }' a4 t- j! _/**** The following comment form also works ****/
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//exemplar attribute nodeA_3 preserve_signal true: q0 z5 ^4 Y; K- W; c# b
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//exemplar attribute nodeA_3 opt keep9 E1 ^1 ^& D2 ^; k1 K
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/**** The following comment form also works ****/% B' S. H" B! n/ k" Z6 k
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//exemplar attribute nodeA_2 preserve_signal true9 W) _/ t- z& f4 ~9 T9 p* n
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//exemplar attribute nodeA_2 opt keep
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' o4 ~* J; V8 y5 l/ u5 V4 l6 f/**** The following comment form also works ****/9 q* B U- v$ }" I# Y
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//exemplar attribute nodeA_1 preserve_signal true) J6 o0 O$ Z" {
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//exemplar attribute nodeA_1 opt keep
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/**** The following comment form also works ****/
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0 N. m3 t2 D* [0 A' Q2 l0 ?/*exemplar attribute nodeA_0 preserve_signal true
6 }* ^$ r2 Y* w) U8 K. S+ m p' u, G1 Q! C6 X. p _- x+ l9 p7 I
exemplar attribute nodeA_0 opt keep*/
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$ E& R& t3 o6 s8 l: q( g, v! mwire nodeA/* synthesis syn_keep=1 opt="keep"*/;( P5 c3 e; Y0 l! v$ }- X' K
wire nodeA_0/* synthesis syn_keep=1 opt="keep"*/;/ U( O) A% |+ H
wire nodeA_1/* synthesis syn_keep=1 opt="keep"*/;
! F. e2 t, P8 X' y X6 ]$ Nwire nodeA_2/* synthesis syn_keep=1 opt="keep"*/;
4 M, }& F5 j8 K Fwire nodeA_3/* synthesis syn_keep=1 opt="keep"*/;1 c v. T( r: A4 w! Z
wire nodeA_4/* synthesis syn_keep=1 opt="keep"*/;
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assign#1 nodeA_0 = sclk & ena;
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assign#1 nodeA_1 = ~ nodeA_0;
5 H7 v3 }, v. V0 W5 s! V7 R' Jassign#1 nodeA_2 = ~ nodeA_1;
& E. s7 |. m$ j8 i2 uassign#1 nodeA_3 = ~ nodeA_2;- c" j& {3 Y( @. a- z% b
assign#1 nodeA_4 = ~ nodeA_3;
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* W' _" N' r# A) k4 M6 E) F, kreg xout;: i( D5 ]+ e ~* S" _3 t; A) U
" N2 S$ d7 H0 Z- ^always@(nodeA_1,nodeA_2,nodeA_3,nodeA_4,set)
5 ^) _$ Q! O8 i# F3 g! d casez(set)
9 n: F% f' k( u" o+ u. | 1: xout =#1 nodeA_2;
( k$ A' @8 e; a5 u2 F 2: xout =#1 nodeA_3;: M6 V/ S: v) c r s
3: xout =#1 nodeA_4;! r" q7 _8 w2 T, ~5 x t
default: xout =#1 nodeA_1;
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assign#1 nodeA = xout;
! _. s! u; B- x" B/ kassign#1 outp = ena ? nodeA^sclk : 1'bz;) n0 X) |2 v% [; D
5 J/ Z0 [( v; { _endmodule2 Y c& I* [) K( {9 `! R
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6 O. v( a F7 E4 l) b* v+ O`timescale 1 ns / 1 ns/ w% E [6 }! F8 X4 ~1 o
module xclk_tf();
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// Inputs% O! H7 I" A: C" t
reg sclk;8 I8 ?4 k& h9 s9 V5 S
reg ena;: W6 G |. F" |/ _7 |
reg [1:0] set;
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// Outputs/ f ]: t K8 r& o3 G
wire outp;/ C5 o1 i4 a8 [, S9 k
6 j& _% c1 H% c& A7 F( s+ {6 Y. x3 ~
: @; U Q, p, f. t4 P. X xclk UUT (
7 N* Y: t) i3 Z9 N) `- r .sclk(sclk),
7 y9 k, f9 n0 k) Y* H5 T8 x .ena(ena), " H& [3 { z/ O8 N+ ^" M
.set(set),
6 e# V1 O8 w: Y( T1 R3 B .outp(outp)( X' Z; R2 M) Y6 v# o" W8 Y
);
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initial begin# I# l! W% W% y+ j& T; s2 |( v& [8 [
sclk = 0;
! s, ?- C" z7 ~% z# t ena = 0;
- b! j: s5 |) N2 r: w set = 0;3 x0 \# l1 _ B ^8 j- w
end2 V; ^, @: r5 l) a2 a: j
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; x5 W9 f7 e8 V+ P, u5 W2 y* D7 Ralways# 5 sclk = !sclk;% ]* r9 `- u+ P* v& T! ~
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initial begin# n2 b& ]9 N$ Z9 y
#100
% E5 c# P- e' F4 i ena = 1;
V7 ^1 c2 Z& u #2000 , b( y$ ?; l; ~! Q& ?. J
set = 2;
" J) s' i3 \/ A0 a/ K' B3 q2 z& l #2000
* o) F9 @! A( a6 l+ ~! W set = 3;$ _9 H5 u% w& A4 a
#20004 W2 s, W4 G0 N- Z
$finish;* c5 E0 s/ ^& K; `4 K( b
end" e# {; X" ? q/ |1 A
endmodule // xclk_tf |
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