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Cadence ==> RTL Compiler + Encounter Test (acquired from IBM) ) X$ ~( i- t6 y
3 J, Q3 L" s- xspecial capability: n. T" k8 G1 T/ T3 V" a
Synopsys : support multiple clock domain, phase shift test clock
6 d! L/ \3 y; D$ D! y8 u+ HMentor : highest compression
. V! r4 }5 d6 V& ~' kCadence : low power handling, pattern fault, diagnostics2 P5 g H I: ~% E6 }
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Common new features:( k, K# P* U1 R7 V
Compression, at-speed ATPG, core wrapper, BIST, IEEE1149.1
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7 A- D2 \% J$ O% y# h% `! B/ eIn my image, Syntest had became a service-oriented company. |
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