11/19-20 Semiconductor Manufacturing Forum 2009

chip123 · 發表於 2009-10-21 17:58:10

由台灣半導體產業協會主辦之「2009半導體製造技術論壇Semiconductor Manufacturing Forum 2009」將於11/19-20於新竹交通大學舉行，會中邀請關於Thin Film、Asembly, Packaging & Testing、Diffusion、Design, Reliability & Testing、Litho與Etching等專家對未來趨勢與新技術進行專題演講，是半導體專業人士不可錯過的一場盛會，即日起開始報名，歡迎各界踴躍參加。

2009/11/19-20 National Chiao Tung University Library International Conference Hall
交通大學浩然國際會議廳

Agenda 議程
Session 1: Thin Film (11/19 13:20-16:20)

: V6 C1 Z) H' P	Topic	Speaker
13:20-14:00% U! }$ V" l, i, r( n" {7 J	Engineering Slurry for Copper Chemical Mechanical Polishing + \| F p+ r. f) i8 D	Dr. Song-Yuan Chang / 3 }4 j4 G. R( U$ p, U/ {; W CTO& senior VP, UWiZ! K8 I! @, z# R' Z b2 o. t* C0 R+ U Technology
14:00-14:408 v j& C5 T/ I0 \1 [# n	Tailoring CMP Consumable Sets To Meet the Increasing Demands Of IC Device Manufacturing For Advanced Nodes	Dr. Fred Sun / Cabot 8 w' R5 x) X; \|: A4 y
14:40-15:003 E6 m4 v- W I$ E: Z	Break 6 [; K' X, \' b/ @9 k5 G	2 O; F! u6 \|" s! k" u
15:00-15:40 3 Z- j3 C, D5 w( s3 b5 K	? 5 \2 f d) m& c; U+ T	Apllied Materials0 E9 `! a8 Q5 h- ^! {* A" h% T
15:40-16:20 0 M+ }. L( d4 K& a. p1 g- C( ]& Q! ]6 E	CMP Fundamentals and Implications for Consumables Design 9 Y% u& ?% a; O- t0 t& _0 i3 o, i	Ms. Kate Kao/ Marketing Manager Dow chemical- r% S9 S6 j R' _5 K! K

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chip123 · 發表於 2009-10-21 18:02:34

Session 6: Etching

! e& B2 U/ V) E' r7 w' o' a) R	Topic , B7 F) P% e2 b. ], P5 \% g	Speaker 1 L7 Q, ~+ Y5 W8 q5 d" D$ h! o
13:20-14:00/ i+ q# G# p& @	The Advantages of real-time wet process monitoring by multi-channel, in-line NIR analyzer ! r5 i0 _" i" Y) X4 R- F6 Z8 I	Mr. Shay Tina / CI Semi , Director of Sales ! a+ k& T( ~2 U" e
14:00-14:407 P" F+ e2 Z" ^0 W! ^, x& M- k	Green Chemistry for current technology and beyond ; r: p3 Z* y }3 l	Mr. Elvis Sheen / Mallinckrodt Baker, Senior Manager( o7 G2 P# X7 a# h
14:40-15:00 6 V! L' U( P/ M9 e _+ O( k	Break 0 P6 c7 q1 X& P( G: A* h* ^	& G3 ^/ x& m' {) _) Y5 ?# J& a
15:00-15:402 q {0 l% o* Y8 k" H8 C6 o	Post-etch residue removal for advanced copper low-k device % I8 L, _3 T% y8 r0 w) \4 ]	Dr. Hisashi Takeda / EKC Technology, DuPont . w) j, y! _% }) a& Z
15:40-16:20 8 y8 V: i: Z6 L4 u) `5 w	Edge Die Yield Improvement with Immersion Lithography Defectivity Control by Bevel Etch Clean: T" ~ D8 N( d$ v( y- u	Lam Research # p* A* R* g: Q: f- P9 T) K" B
16:20-17:003 y0 A: c3 q* \|) r	Improved Control of Through-Silicon Via Profiles for Advanced Packaging Applications7 ]: ]# S1 Z" K: G3 M	Surface Technology Systems- W8 l; \: u( x$ L; \|

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chip123 · 發表於 2009-10-21 18:02:03

Session 5: Litho

1 ~$ N( k: g6 ]1 G, F R# y3 ?. T	Topic; Q) Q6 U$ G. I	Speaker, B+ E8 V- n9 S- x' q6 g) z
13:20-14:00* }1 B0 q# P0 q0 g# `( O	Photomask technology for 32/22nm and beyond 3 ?' U1 t- }& G& s. Z6 P% k* \| h	Dr. Hiroaki Morimoto/Senior General Manager," w, b, S* E' f5 z( `. [( W Toppan Printing% B2 D3 F9 Y+ U5 n1 h5 h
14:00-14:40; i9 t9 O$ j9 S' A4 z6 [	' A2 K8 `# m7 d) m% b Implant Resists for Advanced Node Applications 1 C. d7 G/ n6 a! c; V	Mr. Yoshiro Yamamoto/ " Y! R+ A/ L3 VDUV RD mamager, DOW1 ^ V$ S4 g8 _: }! ` 2 }: ~* y* G' S Semiconductor Technology , c; s* H) }: p$ F* w# L8 t) f6 Q
14:40-15:00 6 }% ]) `* X* d" m7 P% [	Break / C9 C$ l- L/ x2 H8 E	0 o8 L% C! G5 A2 ]* {& ^
15:00-15:40; Q* m6 {: e+ E: D" W	State-Of-The-Art Development of BARC Material a; r; q7 Z; ~' A% U: l- _1 H	Brewer Science! w% j; ]1 v% t$ q" R% U
15:40-16:20 5 }; n7 c- G0 s0 V( X! I	The Future Trend for Next Generation Lithography 4 b; W% ?9 x; \|8 d	ASML 9 F# S" Z% \|/ t. ^
16:20-17:00 0 V* A* h6 b/ v* \/ K; k- J	Future Trend of Track Technology . A) H, Z( }; v: W	TEL) Y1 x) Y& U3 L/ R; A ]- I

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chip123 · 發表於 2009-10-21 18:01:32

Session 4: Diffusion

+ K2 T+ L2 @$ ]	Topic! \1 W- y7 ~ L2 s	Speaker 1 S t% y* q. I/ X8 }8 _; u
9:00-9:40 ! T# A' i' K1 v7 P/ ^; b3 f	Surface Preparation process control requirement to support CMOS scaling into 22nm 4 A4 I0 c1 `* i6 l- c	Dr. Scott Becker/ Vice President, FSI7 \|. d( ~1 N3 g9 L
9:40-10:20 + a6 Z- [' s+ Z: n- F. a: v	Wafer techincal roadmap and application for advanced or special proces - D! t. u7 S7 U! }9 z+ q' f; C7 S	MEMC - m g3 ^5 A( O1 u
10:20-10:40+ f4 l1 S, D; P9 F! s9 _! A	Break & f% p% p$ ^% b9 j	4 L1 q2 Q" @. V* m$ v& ~- R! V3 z+ ~
10:40-11:20 . k: C6 I- u6 y1 e: h- t4 N4 j	# T5 W/ ] y* j	7 E& U& Z( E4 M" V

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chip123 · 發表於 2009-10-21 17:59:56

Session 3: Design, Reliability & Testing

$ I6 B& I6 r& u3 o1 i6 Z0 o	Topic/ m# C, A% h! C V' u	Speaker 9 m# m% D% [8 c" C3 C: m
9:00-9:40 $ L' A- S1 K3 S- }1 _9 @* ?6 o% [	Design Trend? $ X7 {. s' g% k) X0 H	Marketing VP, Dr. Chiang Alchip, L9 `. C- t1 z! u
9:40-10:20 : a# A' }8 c7 X0 Q	Charged-Device-Model (CDM) ESD Protection in CMOS Integrated Circuits 6 W2 F3 K6 @' F' {4 s/ D q	Prof. Ming-Dou Ker / I-Shou Universit ! c: M+ J/ @* U1 {
10:20-10:40& `& j/ K! g( U' \; b& Y	Break 9 j" Q3 c% T2 a- S7 b& z	- U& ]7 M4 P9 s
10:40-11:20	Parametric Test Challenges of the Next Process Frontier ' G1 T# R0 h! E, A$ C- g	Ms. Flory Tsai / agilent 3 T/ \|/ U7 V$ h3 p) N
11:20-12:00/ G0 N8 H$ O6 U& q/ c	Recent Development Work and Trend for Semiconductor Device Characterization ( Z3 c( N0 a; ?& ?, h5 l6 k8 P	AL Feng / 專案經理 / Keithley Taiwan " \: V' c5 R( B& z5 x: A# I$ l

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chip123 · 發表於 2009-10-21 17:59:25

Session 2: Assembly, Packaging & Testing (11/19 13:20-16:20)

3 v& Y7 k* R q {; O b1 B% b/ v	Topic 0 `5 f) y. s! D) }& i. Q	Speaker) _# r/ Y2 T7 @/ \|. C
13:20-14:00 , p2 Q# p& V* E' w# f$ K$ M	Sip Assembly technology?' S/ z: i' y# g3 d' x1 U	Dr. KC Yee/ VP, ASE ) r+ W- e: ~9 Z5 k
14:00-14:40* Z$ o* Z- s+ l0 f& m; g7 y; c( i	Assembly trend from perspective/ D% k# X: v. x7 ~	邱世冠資深經理/矽品 : t/ W3 _ E9 O" `1 H, V5 _前瞻科技中心8 h7 J" k+ y4 ~7 P1 c
14:40-15:00, A4 S) i$ H; z$ m% E1 _	Break! \|/ m( L# L9 m	# r- ]: }* j: s" m" V
15:00-15:40) C% a2 l# v Z5 K	The Paradise of Cost-Effective Wafer Probing Technology, ]4 E' \|, q3 k: L: d- ?- {	Dr. CCNi / Associate Director , KYEC6 D0 L4 G$ C5 G) C1 ^
15:40-16:20$ U, E4 D: h( t. x, _' B+ B5 \* i	RF SOC /Sip? 5 K% k$ b* e6 V! A4 ?	Verigy! q! l+ W$ n* w& _( z Z: ]

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