verilog 觸發的問題

scroll529 · 發表於 2009-3-26 19:44:35

請問....
always (*)
   begin
   if(!rstn) r1 = r2 + r3 ;
   else    r1 = r5 << 4;
   end
請問*是表示r2.r3.r5的意思嗎,如果是像這樣子的寫法是否能夠合成

   小弟才疏學淺...謝謝各位大大

賈斯丁 · 發表於 2009-4-28 12:44:19

Verilog-2001 added the much acclaimed @* combinational sensitivity list. The primary intent of this enhancement
was to create concise, error-free combinational always blocks. The @* basically means, "if Synopsys DC wants the
combinational signal in the sensitivity list, so do we!"
Example 1 and Example 2 show the Verilog-1995 and Verilog-2001 versions respectively of combinational
sensitivity lists for the combinational always block of any of the three always block fsm1 coding styles.

always @(state or go or ws)
begin
...
end
//Example 1

always @*
begin
...
end
//Example 2

The @* combinational sensitivity list as defined in the IEEE Verilog-2001 Standard can be written with or without
parentheses and with or without spaces as shown in Example 3. Unfortunately (* is the token that is used to open
a Verilog-2001 attribute, so there is some debate about removing support for all but the always @* form of this
combinational sensitivity list. In-house tools would probably also be easier to write if the in-house tools did not
have to parse anything but the most concise @* form. For these reasons, I recommend that users restrict their usage
of the combinational sensitivity list to the @* form.
always @*
always @ *
always @(*)
always @ ( * )
//Example 3

masonchung · 發表於 2009-4-22 18:30:29

這個是 verilog 2001 的語法喔

videochip · 發表於 2009-4-17 18:46:58

可以合成 !!
不過應該是這樣吧

always @(*)
   begin
   if(!rstn) r1 = r2 + r3 ;
   else    r1 = r5 << 4;
   end

spring69393 · 發表於 2009-4-4 08:50:12

敏感列是只要那個變數有變化，就重新判斷一次， * 應該是沒有效果才對，
你這樣寫法應該會造成出來的值是跟你所要的不同結果。

newwalkman · 發表於 2009-3-31 19:57:31

敏感表中不仅是要传送的值(r2,r3,r5),还包括判断条件(rstn)

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[問題求助] verilog 觸發的問題