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AMD Geode LX 800@0.9W處理器
General Features
8 c6 H! m! c% i3 d0 U4 T■ Functional blocks include:
v d' x6 F! u. P/ X; P— CPU Core
' ?9 B* ?- R* P5 b$ A" z A— GeodeLink™ Control Processor: s$ s) a6 x3 M+ a
— GeodeLink Interface Units1 H6 s( M7 f: M0 P" a* v
— GeodeLink Memory Controller8 @/ `( E/ J% J. h% P+ h% I
— Graphics Processor
1 g: c% z5 d7 c3 |9 o5 H— Display Controller( A* k2 V7 I+ y. e
— Video Processor) |& O, p+ r9 F+ C, e9 J8 a
– TFT Controller/Video Output Port
' `, r+ D; ` H, R2 A5 L i— Video Input Port" D; G2 `) b9 J! a' [
— GeodeLink PCI Bridge3 Q4 E, G/ Y! ^! ~: }- ^0 L* ~3 i
— Security Block/ t: j- w }1 N8 {$ D
■ 0.13 micron process0 j- S) Y8 v2 D) B# O" O3 I; L
■ Packaging:
+ R4 D, C& y# _, l8 A$ _2 o— 481-Terminal BGU (Ball Grid Array Cavity Up) with5 u1 {9 r: y7 S
internal heatspreader
8 U/ c% S6 v& I" Y% R! u■ Single packaging option supports all features
2 [! y" Z. S" [3 ?* a O* TCPU Processor Features$ {8 A* a! u+ O2 O2 Y) U
■ x86/x87-compatible CPU core% L% P8 T3 Z, E1 E7 q7 y( I* r
■ Performance:/ ^0 x1 }' N( `2 u j, Y. W8 W( a9 ^
— Processor frequency: up to 500 MHz- h6 J2 d( N3 F- h& Z
— Dhrystone 2.1 MIPs: 150 to 450
$ ^# v: H; ?6 g— Fully pipelined FPU
f( z1 w6 l( C# w1 ]3 ~$ `■ Split I/D cache/TLB (Translation Look-aside Buffer):
/ m+ Q# {. i1 u% U- L" Y& |6 F/ C— 64 KB I-cache/64 KB D-cache
5 D, d" @% ^6 ^— 128 KB L2 cache configurable as I-cache, D-cache,
3 Q9 n0 P! K1 Z9 {+ |1 h1 S+ R' zor both4 ]" d U& Q7 F2 H0 u# S
■ Efficient prefetch and branch prediction
% y3 p X7 [' S0 S0 U2 e■ Integrated FPU that supports the MMX® and
, a' G2 J9 j4 wAMD 3DNow!™ instruction sets0 l8 R. _( P* L
■ Fully pipelined single precision FPU hardware with
7 p5 Z* F% Y: p% z4 f nmicrocode support for higher precisions. z5 Z/ A" b( _
GeodeLink™ Control Processor$ k' }" j+ _ a7 e8 g% R ]* G
■ JTAG interface:
" E/ g. o: ?3 k/ s' j& S: X: ^/ \$ @— ATPG, Full Scan, BIST on all arrays
\; q1 N& f1 b8 D9 L2 R— 1149.1 Boundary Scan compliant
. p( @) T5 F: Z/ ]9 Y■ ICE (in-circuit emulator) interface
7 c+ J. |! m3 G( N1 ]1 ^0 [■ Reset and clock control
/ f; _2 t+ T' t. F* s8 g6 q■ Designed for improved software debug methods and
% Q( { W q& L) Vperformance analysis
1 g- {9 k; ?' K7 f& {/ q, A■ Power Management:
, X8 v) m) l2 B! i' v— Total Dissipated Power (TDP) 3.8W, 1.6W typical @$ g; h8 h* j. F* c) s/ |" b
500 MHz max power
9 Y0 k: [0 d' o— GeodeLink active hardware power management
* J, R" S6 R. k7 [8 R% ]! u— Hardware support for standard ACPI software power# R2 _/ k" n7 ?% o7 {
management
3 Y6 x( g+ `6 S8 t+ l9 {" F— I/O companion SUSP/SUSPA power controls
- M% d+ y9 f; U, H— Lower power I/O
9 _8 Q# w( V8 q— Wakeup on SMI/INTR
1 v+ ]/ [+ |) U■ Designed to work in conjunction with the
& E, t s9 [1 J/ y0 l" G1 v% k' MAMD Geode™ CS5536 companion device
3 |4 p1 V) p1 h/ OGeodeLink™ Architecture
9 ?0 H: K( x3 ]7 Y7 V■ High bandwidth packetized uni-directional bus for0 j7 V) l% E( P
internal peripherals+ R5 G8 i/ m( \" x7 K$ Y: @
■ Standardized protocol to allow variants of products to be1 K, m7 J) W0 s9 e- A* `2 c
developed by adding or removing modules
+ [2 q2 ~4 F+ \2 J7 i■ GeodeLink Control Processor (GLCP) for diagnostics
* b; G5 K! m( I0 Dand scan control
: Y' G; p- u' M% p* Y■ Dual GeodeLink Interface Units (GLIUs) for device interconnect
+ `) q$ [$ b4 N; V% y6 I$ H+ MGeodeLink™ Memory Controller
a8 v2 ^9 K; {6 Y# g■ Integrated memory controller for low latency to CPU and* w. w$ y7 F* p5 y* k) r, G# g2 s1 h
on-chip peripherals
{/ A! _1 G" m) {■ 64-bit wide DDR SDRAM bus operating frequency:- L9 }) Y& F' j$ r; e/ R) h
— 200 MHz, 400 MT/S
; L5 p2 U, C; T% ~■ Supports unbuffered DDR DIMMS using up to 1 GB! J! d: I4 q& ]' _
DRAM technology, t Z" F% W$ b7 V: }
■ Supports up to 2 DIMMS (16 devices max)4 T8 d/ c& C5 {' A* c( x: W
2D Graphics Processor* B9 G2 G- F; b& P
■ High performance 2D graphics controller! j1 n: @! B- G9 L
■ Alpha BLT
; W7 K' @4 N! ^* j) J■ Microsoft® Windows® GDI GUI acceleration:
& ^* s& ]/ }$ G( }— Hardware support for all Microsoft RDP codes
3 q, I7 I" W% u2 D■ Command buffer interface for asynchronous BLTs0 l9 A+ o- H+ H( @5 d
■ Second pattern channel support
4 {1 U/ E7 x6 h% A, V■ Hardware screen rotation |
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發表於 2007-2-6 18:17:18
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