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Senior Physical Design Engineer8 Q7 U- e: c3 d8 k1 z3 k
公 司:A famous IC company& P' _6 R' S% q1 C5 y) k
工作地点:南京
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* K& ]- h: X a% t3 D% hKey Responsibilities
; m8 i0 A+ T& i rDepending on experience, key responsibilities will involve some of the following:
, N' D; g* b2 @6 BIC implementation from netlist to gdsii, with synthesis, floorplanning, place and route, timing closure, and physical verification.
/ z+ k* V4 {2 J8 ]As a key member of physical design team, your will work on one of most advanced and the most complex chip designed.
. \# m9 e2 @8 I- i! BLeading a team of physical design engineers and resolving the technical related issues. 3 g e7 z; Q$ [1 M6 z
Crosstalk analysis, power analysis, and static timing analysis. . b; {, n+ ]7 [
Write scripts in Tcl to improve productivity.
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Experience: 5+ years in physical implementation engineering 6 X; x0 I0 B) |8 c" Z: u0 `
4 z/ I1 G- {" y, c5 X7 r1 yEssential skills . Q8 E& ^$ y3 A3 C* p3 R) y6 x
MS in EE required.&#8226 roven track records of working independently on place-and-route project running and DRC/LVS/ERC/Antenna debugging skills % H( l0 E) a W6 {
Experience with Magma or Synopsys place-and-route tool set and physical design project implementation.
, \; ~9 P i' [! cGood programming skill. Capable of writing Tcl or Perl.
+ a9 T1 c! X$ g+ x0 \' tFamiliar with synthesis, static timing analysis. ! A/ F% ?) K4 F, b" X1 `' ^
Self-motivated team worker, good verbal and written communication skills in English.
! P) ~4 Z4 i: }, GTechnical and team leadership proffered. Previous management experience highly desired. 2 c' A# q' n1 N, E4 N1 _* w
Experience with synthesis, DFT, and verification is preferred. |
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